3D Chip stacking with 50 μm pitch lead-free micro-c4 interconnections

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 268-273

  Maria, J ^a   Dang, B ^a   Wright, S L ^a   Tsang, C K ^a   Andry, P ^a   Polastre, R ^a   Liu, Y ^a   Wiggins, L ^a   Knickerbocker, J U ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ASSEMBLY YIELDS; BONDING PARAMETERS; CHIP STACKING; COMPRESSION MODE; FINE PARTICLES; FORM FACTORS; HIGH DENSITY; JOINING PROCESS; JOINT FORMATION; JOINT RELIABILITY; LEAD-FREE; MICRO-BUMPS; MULTIPLE BONDING; MULTIPLE LAYERS; NARROW GAP; PARASITIC RESISTANCES; PB FREE SOLDERS; SILICON DIE; TEMPERATURE PROFILES; TEST VEHICLE; THERMAL CYCLING TEST; UNDERFILLING; UNDERFILLS;

APPROXIMATION THEORY; DIES; RELIABILITY;

THREE DIMENSIONAL;

EID: 79960402562     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898524     Document Type: Conference Paper

References (11)

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