Design and process of 3D MEMS system-in-package (SiP)

Journal of Microelectronics and Electronic Packaging

Volumn 7, Issue 1, 2010, Pages 10-15

  Lau, John H ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

3D IC integration; Low tempera ture bonding; MEMS; SiP; TSV; Wafer level packaging

Indexed keywords

ASSEMBLY; CHIP SCALE PACKAGES; DESIGN; ELECTRONICS PACKAGING; ETCHING; FLIP CHIP DEVICES; INTEGRATED CIRCUIT DESIGN; INTEGRATED CIRCUIT MANUFACTURE; MEMS; SILICON WAFERS; SYSTEM-IN-PACKAGE; WAFER BONDING;

ASSEMBLY PROCESS; CAVITY ETCHING; DESIGN AND ASSEMBLIES; ELECTRICAL PERFORMANCE; SINGULATION; THROUGH-SILICON-VIA; WAFER LEVEL PACKAGING; WIRE BONDING;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 84856484569     PISSN: 15514897     EISSN: None     Source Type: Journal    
DOI: 10.4071/1551-4897-7.1.10     Document Type: Article

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