Development of super thin TSV PoP

2010 IEEE CPMT Symposium Japan, ICSJ10

Volumn , Issue , 2010, Pages

  Carson, Flynn ^a   Ishibashi, Kazuo ^b   Yoon, Seung Wook ^d   Marimuthu, Pandi Chelvam ^d   Shariff, Dzafir ^c  

^a STATS ChipPAC Ltd   (United States)

^b Nokia Japan   (Japan)

^c STATS CHIPPAC LTD   (Singapore)

^d NONE

Author keywords

[No Author keywords available]

Indexed keywords

BUMP PITCHES; DESIGN STAGE; DIE SIZE; ELECTRICAL SIMULATION; FLIP CHIP; LOGIC PROCESSOR; MARKET NEEDS; MATERIAL PROPERTY; MEMORY DEVICE; MOBILE PHONE PLATFORMS; ORGANIC SUBSTRATE; SHARED MEMORIES; SI-BASED; STACKED PACKAGE; TEST VEHICLE; THERMAL SIMULATIONS; THROUGH-SILICON-VIA; TWO PROCESSORS; WARPAGES;

DIES; FLIGHT DYNAMICS; FLIP CHIP DEVICES; MOBILE PHONES; SUBSTRATES; TELECOMMUNICATION EQUIPMENT; TELEPHONE; TELEPHONE SETS;

PACKAGING;

EID: 79251589652     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CPMTSYMPJ.2010.5679652     Document Type: Conference Paper

References (2)

1. Carson, F., Ishibashi, K., Kim, Y.C., " Three-tier PoP Configurarion Utilizing Flip Chip Fan-in PoP Bottom Package", ECTC 2009.
2. Ishibashi, Kazuo, "PoP board assembly in mobile devices", SEMI Technology Symposium (STS), Semicon Japan Dec 2008.