Evaluation of thin wafer processing using a temporary wafer handling system as key technology for 3D system integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1385-1392

  Zoschke, K ^a   Wegner, M ^a   Wilke, M ^a   Jurgensen N ^a   Lopper, C ^a   Kuna, I ^a   Glaw, V ^a   Roder J ^b   Wunsch O ^b   Wolf, M J ^a   Ehrmann, O ^a   Reich, H ^a  

^a FRAUNHOFER IZM   (Germany)

^b TECHNISCHE UNIVERSITÄT BERLIN   (Germany)

Author keywords

[No Author keywords available]

Indexed keywords

3-D SYSTEM INTEGRATION; 3D ARCHITECTURES; CARRIER WAFERS; EVALUATION STUDY; KEY TECHNOLOGIES; MAIN PROCESS; MONITOR WAFERS; PROCESS INTEGRATION; SECOND PHASE; SOLVENT RELEASE; THIN WAFERS; THIRD PHASE; THROUGH-SILICON-VIA; VIA CHAIN; VIA-FIRST; WAFER HANDLING SYSTEMS; WAFER THINNING; WAFER-LEVEL FABRICATION;

DEBONDING; MATERIALS HANDLING; MATERIALS HANDLING EQUIPMENT; SEMICONDUCTING SILICON COMPOUNDS; TECHNOLOGY; THREE DIMENSIONAL; WAFER BONDING;

SILICON WAFERS;

EID: 77955220471     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490637     Document Type: Conference Paper

References (7)

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3. J. Wolf, K. Zoschke, R. Wieland, M. Klein, K.-D. Lang, H. Reichl, "Silicon Interposer for Heterogeneous Integration", Proc. SMTA Pan Pacific, January 26-28, 2010, Hawaii, USA
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6. K. Zoschke, J. Wolf, "TSV silicon interposer technology for 3D wafer level system integration -technological\milestones and challenges-", Proc. 30th Tokyo OHKASeminar, December 1st, 2009, Tokyo, Japan, pp. 31-53
7. K. Zoschke, J. Wolf, O. Ehrmann, H. Reichl, "Temporary Wafer Bonding for Wafer Thinning and BacksideProcessing-Key Technology for 3D System Integration", Proc. 2nd IEEE Workshop on Low Temperature Bonding for 3D Integgration, January 19-20, 2010, Tokyo, Japan, pp. 331-354