Interfacial reliability and micropartial stress analysis between TSV and CPB through NIT and MSA

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1436-1443

  Lee, Gyujei ^a   Kim, Yu Hwan ^a   Jeon, Suk Woo ^a   Byun, Kwang Yoo ^a   Kwon, Dongil ^b  

^a Hynix Semiconductor Inc   (South Korea)

^b Seoul National University   (South Korea)

Author keywords

3DI (3 dimensional integration); Grain growth model; Micropartial residual stress; NIT (nanoinstrumented indentation testing); TSV (through silicon via)

Indexed keywords

3D APPLICATION; 3DI (3-DIMENSIONAL INTEGRATION); BARKHAUSEN NOISE; COMPLICATED STRUCTURES; COPPER PILLARS; CURVATURE METHOD; DESTRUCTIVE TECHNIQUES; HOLE-DRILLING; INDENTATION TESTING; INTERFACIAL RELIABILITY; INTERFACIAL STRESS; MICRO-ELECTRONIC DEVICES; MICRO-SCALES; MICROPARTIAL RESIDUAL STRESS; NIT (NANOINSTRUMENTED INDENTATION TESTING); NON-DESTRUCTIVE TECHNIQUE; PACKAGING TECHNOLOGIES; PROCESSING CONDITION; QUANTITATIVE DESIGN; RELIABILITY PROBLEMS; STACKED STRUCTURE; STONEY EQUATION; STRESS-INDUCED; THROUGH-SILICON-VIA; XRD;

ELASTIC MODULI; ELECTRONICS PACKAGING; FINITE ELEMENT METHOD; GRAIN GROWTH; ION BEAMS; IONS; LOAD TESTING; MICROELECTRONICS; RESIDUAL STRESSES; STRESS ANALYSIS; STRESS CONCENTRATION; STRUCTURAL DESIGN; TECHNOLOGY; X RAY DIFFRACTION;

RELIABILITY ANALYSIS;

EID: 79960415866     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898700     Document Type: Conference Paper

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