Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30m pitch lead-free solder micro bumps and reliability characterization

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 14-21

  Zhan, Chau Jie ^a   Juang, Jing Ye ^a   Lin, Yu Min ^a   Huang, Yu Wei ^a   Kao, Kuo Shu ^a   Yang, Tsung Fu ^a   Lu, Su Tsai ^a   Lau, John H ^a   Chen, Tai Hong ^a   Lo, Robert ^a   Kao, M J ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY PROCESS; BONDED WAFERS; BONDING CONDITIONS; BONDING PROCESS; CHIP STACKING; CHIP-ON-CHIP; CURRENT STRESS; ELECTROMIGRATION RESISTANCE; FABRICATION THROUGHPUT; FLIP CHIP BUMPS; FLUXLESS; GAP CONTROL; HIGH FLEXIBILITY; LEAD FREE SOLDERS; MECHANICAL EVALUATION; MICRO-BUMPS; MICRO-JOINT; PLASMA PRE-TREATMENT; PLASMA TREATMENT; RELIABILITY CHARACTERIZATION; RELIABILITY PERFORMANCE; RELIABILITY TEST; SOLDER MATERIAL; TEST CHIPS; THERMO COMPRESSION BONDING; UNDER-BUMP METALLURGIES; UNDERFILLS; WELL-ALIGNED;

FLIP CHIP DEVICES; INTEGRATION; PLASMA APPLICATIONS; RELIABILITY; THREE DIMENSIONAL; TIN;

WAFER BONDING;

EID: 79960427741     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898484     Document Type: Conference Paper

References (8)

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