Three chips stacking with low volume solder using single re-flow process

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 884-888

  Khan, Navas ^a   Wee, David Ho Soon ^a   Chiew, Ong Siong ^a   Sharmani, Cheryl ^a   Lim, Li Shiah ^a   Li, Hong Yu ^a   Vasarala, Shekar ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

3-D PACKAGES; 3D PACKAGING; ASSEMBLY YIELDS; CHIP-TO-CHIP STACKING; FINE PITCH; FLIP CHIP ASSEMBLIES; FLOW PROCESS; HIGH-FREQUENCY APPLICATIONS; LEAD FREE SOLDERS; MICRO-BUMPS; PERMANENT JOINTS; SINGLE-STEP; STACKING PROCESS;

FLIP CHIP DEVICES; LEAD; THREE DIMENSIONAL; TIN;

CHIP SCALE PACKAGES;

EID: 77955184076     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490686     Document Type: Conference Paper

References (7)

1. Sakuma et al, "3D Chip Stacking Technology with Low-Volume Lead-Free Interconnections," Proc. ECTC 2007, pp. 627.
2. Aibin Yu et al, "Three Dimensional Interconnects with High Aspect Ratio TSVs and Fine Pitch Solder Microbumps," ECTC 2009, pp350-354.
3. Navas Khan et al," Development of 3D Silicon Module with TSV for System in Packaging," ECTC 2008, pp550-555
4. Kurita et al, "A 3D Stacked Memory Integrated on a Logic Device Using SMAFTI Technology," Proc. ECTC 2007, pp. 821.
5. Rahul Agarwal et al, "High Density Cu-Sn TLP Bonding for 3D Integration," ECTC2009, pp.345.
6. Won Kyoung Choi et al "Development of Novel Intermetallic Joints using Thin Film Indium Based Solder" ECTC 2009, pp 333
7. Li Song et al, "Wetting Dynamics Study of Sn-Ag Solder during Reflow," High Density Micro-system Design and Packaging and Component Failure Analysis, 2005, pp1-4