Integration of fine-pitched Through-Silicon Vias and Integrated Passive Devices

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 844-848

  Shariff, Dzafir ^a   Marimuthu, Pandi Chelvam ^a   Hsiao, Ken ^a   Asoy, Lily ^a   Yee, Chia Lai ^a   Oo, Aung Kyaw ^a   Buchanan, Keith ^b   Crook, Kath ^b   Wilby, Tony ^b   Burgess, Steve ^b  

^a STATS CHIPPAC LTD   (Singapore)

^b SPTS Ltd   (United Kingdom)

Author keywords

[No Author keywords available]

Indexed keywords

ACCELERATED STRESS; HETEROGENEOUS SYSTEMS; HIGH TEMPERATURE STRESS; INTEGRATED PASSIVE DEVICE; RE-DISTRIBUTION; RELIABILITY TESTING; RF FILTERS; SOLDER BUMP; THROUGH SILICON VIAS;

ELECTRONICS PACKAGING; SILICON WAFERS;

INTEGRATION;

EID: 79960387146     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898609     Document Type: Conference Paper

References (4)

1. Carson F. et al, "Development of Super Thin TSV PoP" Proc IEEE CPMT Symposium, Tokyo, Japan, 24-26 August, 2010.
2. Motoyoshi M., "Through Silicon Via (TSV)", Proc IEEE, Vol. 97, No. 1, January 2009
3. Logan E. A. et al, "Advanced Packaging of Integrated Passive Devices for RF Applications", Proc IEEE Radio and Wireless Conference, Colorado Springs, USA, 9-12 August 1998
4. Laivron C. et al, "Via First Approach for Through Silicon Via Applications" Proc IEEE Electronic Components and Technology Conference [ECTC], 2009