Process characterization vehicles for 3D integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1112-1116

  Campbell, David V ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; COMPARISON STUDY; INTEGRATION METHOD; MULTIPLE PROCESSING; PROCESS CHARACTERIZATION; PROCESS DATA; PROCESSING STEPS; TEST STRUCTURE; WAFER LEVEL;

ASPECT RATIO; THREE DIMENSIONAL;

DIES;

EID: 77955200508     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490841     Document Type: Conference Paper

References (2)

1. Theodore A. Dellin; William M. Miller; Donald G. Pierce; Eric S. Snyder, "Wafer Level Reliability", Proc SPIE Vol1802, 1993, p. 144-154.
2. Nobuaki Miyakawa, "A 3D Prototyping Chip based on a wafer-level Stacking Technology", Honda Research Institute Japan Co. Ltd..