Wafer level warpage modeling methodology and characterization of TSV wafers

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1196-1203

  Che, F X ^a   Li, H Y ^a   Zhang, Xiaowu ^a   Gao, S ^a   Teo, K H ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ANNEALING PROCESS; ANNEALING TEMPERATURES; AS ANNEALING; BENDING STRESS; DEVELOPED MODEL; ELECTRONIC PACKAGING; EXPERIMENT DATA; MATERIAL MODELS; MODELING METHODOLOGY; NUMERICAL RESULTS; SIMULATION RESULT; SUBMODELING; THREE-DIMENSIONAL (3D); THROUGH-SILICON-VIA; WAFER BENDING; WAFER LEVEL; WAFER STRESS; WAFER SURFACE; WAFER WARPAGE; WARPAGES;

ANNEALING; FINITE ELEMENT METHOD; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; SIMULATED ANNEALING; THREE DIMENSIONAL;

ELECTRONICS PACKAGING;

EID: 79960398905     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898662     Document Type: Conference Paper

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