Thru silicon via stacking & numerical characterization for multi-die interconnections using full array & very fine pitch micro C4 bumps

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 296-303

  Au, K Y ^a   Beleran, J D ^a   Yang, Y B ^a   Zhang, Y F ^a   Kriangsak, S L ^a   Wilson, P L Ong ^a   Drake, Y S Koh ^a   Toh, C H ^a   Surasit, C ^a  

^a United Test and Assembly Center Ltd UTAC   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

ASSEMBLY PROCESS; BACK-END ASSEMBLY; BILL OF MATERIALS; DIE STACK; DIE STACKING; DRIVING FORCES; FINE PITCH; FLIP CHIP; FULLY INTEGRATED; FUNDAMENTAL CHANGES; FUTURE TRENDS; HIGH-VOLUME PRODUCTION; LOW COSTS; MANUFACTURABILITY; MASS PRODUCTION; MATERIAL PROPERTY; MULTI-FUNCTIONAL; MULTIPLE DEVICES; NUMERICAL CHARACTERIZATION; ORGANIC SUBSTRATE; PACKAGING TECHNOLOGIES; PROCESS VERIFICATIONS; RELIABILITY TEST; RELIABLE PERFORMANCE; SILICON DIE; THROUGH-SILICON-VIA;

ASSEMBLY; CHIP SCALE PACKAGES; FINITE ELEMENT METHOD; RELIABILITY ANALYSIS; SUBSTRATES;

DIES;

EID: 79960391251     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898529     Document Type: Conference Paper

References (3)

1. J. U. Knickerbocker, P. S. Andry, B. Dang, R. R. Horton, C. S. Patel, R. J. Polastre, K. Sakuma, E. S. Sprogis, C. K. Tsang, B. C Webb, and S. L. Wright "3D Silicon Integration" IBM T. J. Watson Research Center, ECTC 2008, pp. 538-543
2. D. Y. Chen et al, "Enabling 3D-IC foundry technologies for 28nm node and beyond: through-silicon-via integration with high throughput die-to-wafer stacking", IEEE 2009, pg 14.3.1-14.3.4.
3. K. Y. Au, S. L. Kriangsak, X. R. Zhang, W. H. Zhu and C. H. Toh, "3D Chip Stacking & Reliability using TSV-Micro C4 Solder Interconnection" , United Test and Assembly Center Ltd (UTAC), ECTC 2010, pp. 1376-1384.