메뉴 건너뛰기




Volumn , Issue , 2011, Pages 861-868

Characterization of the thermal impact of Cu-Cu bonds achieved using TSVs on hot spot dissipation in 3D stacked ICs

Author keywords

[No Author keywords available]

Indexed keywords

3-D ICS; ELECTRONIC SYSTEMS; EXPERIMENTAL SETUP; HIGHER TEMPERATURES; HOT SPOT; INTERCONNECT STRUCTURES; PERFORMANCE ENHANCEMENTS; STACKED DIE; TEMPERATURE PEAKS; TEMPERATURE PROFILES; TEST CHIPS; THERMAL BEHAVIORS; THERMAL HEATERS; THERMAL IMPACTS; THERMAL MODEL; THERMAL SPREADING; THERMALLY CONDUCTIVE ADHESIVES;

EID: 79960420837     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898612     Document Type: Conference Paper
Times cited : (20)

References (25)
  • 1
    • 50249088167 scopus 로고    scopus 로고
    • The rise of the 3rd dimension for system integration
    • Beyne, E. "The Rise of the 3rd Dimension for System Integration", Proc. IEEE IITC, pp. 1-5, 2006.
    • (2006) Proc. IEEE IITC , pp. 1-5
    • Beyne, E.1
  • 6
    • 2342646748 scopus 로고    scopus 로고
    • Structure function evaluation of stacked dies
    • March 9-11, San Jose, CA, USA
    • Rencz, M.; Székely V.; "Structure function evaluation of stacked dies", Proceedings of the XXth SEMI-THERM Symposium, March 9-11, San Jose, CA, USA, pp 50-55, 2004.
    • (2004) Proceedings of the XXth SEMI-THERM Symposium , pp. 50-55
    • Rencz, M.1    Székely, V.2
  • 10
    • 77949567417 scopus 로고    scopus 로고
    • Analytical and numerical modeling of the thermal performance of three-dimensional integrated circuits
    • March
    • Jain, A.; Jones, R. E.; Chatterjee, R.; Pozder, S.;, "Analytical and Numerical Modeling of the Thermal Performance of Three-Dimensional Integrated Circuits", Components and Packaging Technologies, IEEE Transactions on, vol. 33, no. 1, pp. 56-63, March 2010.
    • (2010) Components and Packaging Technologies, IEEE Transactions on , vol.33 , Issue.1 , pp. 56-63
    • Jain, A.1    Jones, R.E.2    Chatterjee, R.3    Pozder, S.4
  • 11
    • 77952638325 scopus 로고    scopus 로고
    • A novel conduction-convection based cooling solution for 3D stacked electronics
    • Kota, K.; Hidalgo, P.; Joshi, Y.; Glezer, A., "A novel conduction-convection based cooling solution for 3D stacked electronics", SEMI-THERM 2010, pp 33-40.
    • SEMI-THERM 2010 , pp. 33-40
    • Kota, K.1    Hidalgo, P.2    Joshi, Y.3    Glezer, A.4
  • 12
    • 79957642023 scopus 로고    scopus 로고
    • Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects
    • Feb
    • Dang, B.; Bakir, M.; Sekar, D.; Meindl, J.; "Single and 3D chip cooling using microchannels and microfluidic chip input/output (I/O) interconnects", IEEE Trans. Adv. Packaging, vol. 3, no. 1, pp. 79-87, Feb. 2010.
    • (2010) IEEE Trans. Adv. Packaging , vol.3 , Issue.1 , pp. 79-87
    • Dang, B.1    Bakir, M.2    Sekar, D.3    Meindl, J.4
  • 13
    • 70449637149 scopus 로고    scopus 로고
    • Thermal management of vertically integrated packages
    • edited by P. Garrou, C. Bower and P. Ramm Wiley-VCH Verlag GmbH, Weinheim, Part IV
    • Brunschwiler T. and Michel, B.; "Thermal Management of Vertically Integrated Packages", in Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits, edited by P. Garrou, C. Bower and P. Ramm (Wiley-VCH Verlag GmbH, Weinheim, 2008) Vol. 2, Part IV, pp. 635-649.
    • (2008) Handbook of 3D Integration: Technology and Applications of 3D Integrated Circuits , vol.2 , pp. 635-649
    • Brunschwiler, T.1    Michel, B.2
  • 14
    • 15044356680 scopus 로고    scopus 로고
    • Integrated microchannel cooling for three-dimensional circuit architectures
    • Koo, J. M., Im, S., Jiang, L., and Goodson, K. E., 2005, "Integrated Microchannel Cooling for Three-Dimensional Circuit Architectures", ASME Journal of Heat Transfer, Vol. 127, pp. 49-58.
    • (2005) ASME Journal of Heat Transfer , vol.127 , pp. 49-58
    • Koo, J.M.1    Im, S.2    Jiang, L.3    Goodson, K.E.4
  • 17
    • 67649848108 scopus 로고    scopus 로고
    • Thermal resistance measurement of interconnection, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack
    • Matsumoto K., Taira Y.: "Thermal resistance measurement of interconnection, for the investigation of the thermal resistance of a three-dimensional (3D) chip stack", Semi Therm 2009 (25th Semiconductor Thermal Measurement and Management Symposium), pp. 321-328, 2009.
    • (2009) Semi Therm 2009 (25th Semiconductor Thermal Measurement and Management Symposium) , pp. 321-328
    • Matsumoto, K.1    Taira, Y.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.