3D packaging with through silicon via (TSV) for electrical and fluidic interconnections

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2009, Pages 1153-1158

  Khan, Navas ^a   Wai, Yin Hnin ^a   Su, Nandar ^a   Kripesh, Vaidyanathan ^a   Pinjala, ^a   Yu, Li Hong ^a   Pin, Tan Siow ^a   Ho, Soon Wee ^a   Lau, John H ^a,c   Chuan, Toh Kok ^b  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^c HONG KONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (Hong Kong)

Author keywords

[No Author keywords available]

Indexed keywords

3-D PACKAGES; 3D PACKAGING; CHIP CARRIER; COOLING LIQUID; ELECTRICAL INTERCONNECTIONS; FLUIDIC CHANNELS; FLUIDIC INTERCONNECTIONS; HEAT DISSIPATION; HEAT ENHANCEMENT; HERMETIC SEALING; LIQUID COOLING; POP FORMAT; SEALING TECHNIQUE; SILICON CARRIERS; THROUGH-SILICON-VIA; TWO-STACK;

COOLING; HEAT LOSSES; LIQUIDS; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 70349663697     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2009.5074157     Document Type: Conference Paper

References (7)

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