Mitigating heat dissipation and thermo-mechanical stress challenges in 3-D IC using thermal through silicon via (TTSV)

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 411-416

  Onkaraiah, Santhosh ^a   Tan, Chuan Seng ^a  

^a NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

DIELECTRIC ISOLATION; FACE-TO-FACE BONDING; HEAT DISSIPATION; MATERIALS SELECTION; MAXIMUM TEMPERATURE; OXIDE LINERS; SILICON SUBSTRATES; SIMULATION DATA; TEMPERATURE PROFILES; TEMPERATURE REDUCTION; TEMPERATURE RISE; THERMAL MODELING; THERMO-MECHANICAL STRESS; THROUGH-SILICON-VIA;

ELECTRONICS ENGINEERING; INTEGRATED CIRCUITS; STRESSES;

THREE DIMENSIONAL;

EID: 77955178259     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490939     Document Type: Conference Paper

References (7)

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7. S. G. Singh and C. S. Tan, "Impact of thermal through silicon via (TTSV) on the temperature profile of multilayer 3-D device stack", IEEE International Conference on 3D System Integration, San Francisco, September 28-30, 2009.