Implementation of an industry compliant, 5×50μm, via-middle TSV technology on 300mm wafers

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1384-1388

  Redolfi, A ^a   Velenis, D ^a   Thangaraju, S ^a   Nolmans, P ^a   Jaenen, P ^a   Kostermans, M ^a   Baier, U ^a   Van Besien, E ^a   Dekkers, H ^a   Witters, T ^a   Jourdan, N ^a   Van Ammel, A ^a   Vandersmissen, K ^a   Rodet, S ^a   Philipsen, H G G ^a   Radisic, A ^a   Heylen, N ^a   Travaly, Y ^a   Swinnen, B ^a   Beyne, E ^a  

^a IMEC   (Belgium)

Author keywords

[No Author keywords available]

Indexed keywords

300MM WAFER; 65-NM NODE; BOSCH PROCESS; CMOS FABRICATION; CMOS FLOW; CMOS PROCESSS; COMPACT SYSTEM; DENSE STRUCTURES; ELECTROPLATED COPPER; FABRICATION PROCESS; METAL LAYER; PHYSICAL PARAMETERS; PUMPING EFFECT; SILICON SUBSTRATES; THROUGH SILICON VIAS;

CMOS INTEGRATED CIRCUITS; COPPER; ELECTRONIC EQUIPMENT MANUFACTURE; FABRICATION; INTEGRATION; PASSIVATION; SILICON WAFERS; TANTALUM;

ELECTRONICS INDUSTRY;

EID: 79960411500     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898692     Document Type: Conference Paper

References (6)

1. Radisic, A. et al, "Copper Plating of Through-Si Vias for 3D-Stacked Integrated Circuits", Symposium E on Materials and Technologies for 3-D Integration held at the 2008 MRS Fall Meeting, Boston, MA, Dec. 2008, MRS Proc., Vol. 1112, pp. 159-164.
2. Luhn, O. et al, "Monitoring the Superfilling of Blind Holes with Electrodeposited Copper", J. of the Electroch. Soc., Vol. 157, No. 4 (2010), pp. D242-D247.
3. Seppala, E. et al, provisional patent, imec Belgium, 2008.
4. Kwon, H. Y. et al, "Plasma enhanced atomic layer deposition of silicon oxide for through silicon via", 10th International Conference on Atomic Layer Deposition, Seoul, South Korea, Jun. 2010.
5. Mercha, A. et al, "Impact of thinning and through silicon via proximity on high-k/metal gate first CMOS performance", Proc. IEEE Symposium on VLSI Technology, pp. 109-110, Honolulu, HI, US, Jun. 2010.
6. Jourdain, A. et al, "300mm wafer thinning and backside passivation compatibility with temporary wafer bonding for 3D stacked IC applications", IEEE International 3D System Integration Conference - 3DIC, Munich, Germany, Nov. 2010.