Integrated process for silicon wafer thinning

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1811-1814

  Zhou, Shengjun ^a   Liu, Chuan ^b   Wang, Xuefang ^b   Luo, Xiaobing ^b   Liu, Sheng ^a,b,c  

^a SHANGHAI JIAO TONG UNIVERSITY   (China)

^b HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

^c HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

DAMAGED LAYERS; DRY ETCHING PROCESS; EDGE CRACKS; FINE GRINDING; GRINDING PROCESS; HIGH FEED; INTEGRATED PROCESS; LOW COSTS; MATERIAL REMOVAL RATE; MECHANICAL GRINDING; MESH SIZE; ON-WAFER; STRESS RELEASE; THIN SILICON WAFER; THREE DIMENSIONAL SYSTEMS; THROUGH-SILICON-VIA; WAFER THINNING; WAFER WARPAGE; WAFER-THINNING PROCESS;

CHEMICAL MECHANICAL POLISHING; DRY ETCHING; ELECTRONICS PACKAGING; GRINDING (COMMINUTION); GRINDING (MACHINING); GRINDING MILLS; PLASMA ETCHING; SEMICONDUCTING SILICON COMPOUNDS; STRESSES; STRIPPING (REMOVAL); THREE DIMENSIONAL;

SILICON WAFERS;

EID: 79960408272     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898760     Document Type: Conference Paper

References (5)

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5. New, D., "Silicon Thinning and Stacked Packages", SEMI Technology Symposium: International Electronics Manufacturing Technology (IEMT) Symposium, 2002, pp. 50-52.