Reliability study of 3D-WLP through silicon via with innovative polymer filling integration

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 567-572

  Bouchoucha, M ^a,c   Chausse, P ^b   Moreau, S ^b   Chapelon, L L ^a   Sillon, N ^b   Thomas, O ^c  

^a STMICROELECTRONICS   (France)

^b CEA GRENOBLE   (France)

^c AIX MARSEILLE UNIVERSITÉ   (France)

Author keywords

[No Author keywords available]

Indexed keywords

CRITICAL PARAMETER; ELECTRICAL CHARACTERIZATION; ELECTRICAL PERFORMANCE; ELECTRICAL RESISTANCES; ELECTRICAL TESTS; FILLING PROCESS; FINITE ELEMENT MODELLING; HIGH ASPECT RATIO; JEDEC STANDARDS; POLYMER FILLING; POLYMER INSULATION; TEMPERATURE CYCLING; THROUGH-SILICON-VIA; VOID-FREE;

ASPECT RATIO; ELECTRIC INSULATION TESTING; FILLED POLYMERS; FILLING; INNOVATION; RELIABILITY;

POLYMERS;

EID: 79960398916     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898568     Document Type: Conference Paper

References (6)

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3. Bouchoucha, M., et al., Process Solutions and Polymer Materials for 3D-WLP Through Silicon Via Filling. Proceedings IEEE 60th Electronic Components and Technology Conference (ECTC 2010), 2010: p. 1696-8.
4. Charbonnier, J., et al., Development and Characterisation of a 3D Technology Including TSV and Cu Pillars for High Frequency Applications. Proceedings IEEE 60th Electronic Components and Technology Conference (ECTC 2010), 2010: p. 1077-82.
5. JEDEC, JEDEC 22 - A104D, March 2009, in Temperature Cycling.
6. Nix, W., Mechanical properties of thin films. Metallurgical and Materials Transactions A, 1989. 20 (11): p. 2217-2245.