Development of CMOS-process-compatible interconnect technology for 3D-stacking of nand flash memory chips

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 74-78

  Shi, X Q ^a   Sun, P ^a   Tsui, Y K ^a   Law, P C ^a   Yau, S K ^a   Leung, C K ^a   Liu, Y ^a   Chung, C H ^a   Ma, S L ^b   Miao, M ^b   Jin, Y F ^b  

^a HONG KONG APPLIED SCIENCE AND TECHNOLOGY RESEARCH INSTITUTE   (Hong Kong)

^b PEKING UNIVERSITY   (China)

Author keywords

[No Author keywords available]

Indexed keywords

BASIC IDEA; BOND PAD; CMOS COMPATIBLE; CMOS IMAGE SENSOR; FABRICATION PROCESS; IC DESIGNS; INTERCONNECT TECHNOLOGY; MANUFACTURING COST; MICROELECTRONICS PRODUCTS; NAND FLASH MEMORY; THROUGH-SILICON-VIA; VIA INTERCONNECT; WIREBONDING;

DYNAMIC RANDOM ACCESS STORAGE; INTERNET PROTOCOLS; MICROELECTRONICS; NAND CIRCUITS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL; WAFER BONDING;

FLASH MEMORY;

EID: 77955188264     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490884     Document Type: Conference Paper

References (2)

1. Prismark Partners LLC, Market Report on "The Electrics Industry Report", 2009.
2. Yole Development, Market Report on "3D TSV Interconnects - 2008 Edition", 2008.