-
2
-
-
77955218036
-
-
New York, McGraw-Hill
-
J.H. Lau, C.K. Lee, C.S. Premachandran, and A. Yu, "Advanced MEMS Packaging," New York, McGraw-Hill, 2010.
-
(2010)
Advanced MEMS Packaging
-
-
Lau, J.H.1
Lee, C.K.2
Premachandran, C.S.3
Yu, A.4
-
3
-
-
77955210944
-
Critical issues of 3D IC integrations
-
J.H. Lau, "Critical issues of 3D IC integrations," in Proceedings of MAPS International Symposium on Microelectronics, San Jose, CA, 2009, pp. 585-592.
-
(2009)
Proceedings of MAPS International Symposium on Microelectronics, San Jose, CA
, pp. 585-592
-
-
Lau, J.H.1
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4
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77955212579
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Key enabling technologies for 3D IC integrations
-
J.H. Lau, "Key enabling technologies for 3D IC integrations," Professional Development Course, IEEE Electronic it Components Technology Conference, San Diego, CA, 2009.
-
(2009)
Professional Development Course, IEEE Electronic it Components Technology Conference, San Diego, CA
-
-
Lau, J.H.1
-
5
-
-
77955220633
-
Design and process of 3D MUMS packaging
-
J.H. Lau, "Design and process of 3D MUMS packaging," in Proceedings of MAPS International Symposium on Microelectronics, San Jose, CA, 2009, pp. 1-9.
-
(2009)
Proceedings of MAPS International Symposium on Microelectronics, San Jose, CA
, pp. 1-9
-
-
Lau, J.H.1
-
6
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-
77952599293
-
3D LED and IC wafer level packaging
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J.H. Lau, R. Lee, M. Yuen, and P. Chan, "3D LED and IC wafer level packaging," Journal of Microelectronics International, Vol. 27, No. 2, pp. 98-105, 2010.
-
(2010)
Journal of Microelectronics International
, vol.27
, Issue.2
, pp. 98-105
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Lau, J.H.1
Lee, R.2
Yuen, M.3
Chan, P.4
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7
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70349666726
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Thermal management of 3D IC integration with TSV (through silicon via)
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J.H. Lau and G. Tang, "Thermal management of 3D IC integration with TSV (through silicon via)," in IEEE Proceedings of Electronic, Components and Technology Conference, San Diego, 2009, pp. 635-640.
-
(2009)
IEEE Proceedings of Electronic, Components and Technology Conference, San Diego
, pp. 635-640
-
-
Lau, J.H.1
Tang, G.2
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8
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77955205984
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TSV manufacturing yield and hidden costs for 3D 1C integration
-
J.H. Lau, "TSV manufacturing yield and hidden costs for 3D 1C integration," in IEEE Proceedings of Electronic, Components & Technology Conference, Las Vegas, NV, 2010, pp. 1031-1041.
-
(2010)
IEEE Proceedings of Electronic, Components & Technology Conference, Las Vegas, NV
, pp. 1031-1041
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-
Lau, J.H.1
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9
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79951892774
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State-Of-The-Art and trends in 3D integration
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J.H. Lau, "State-of-the-art and trends in 3D integration," Chip Scale Review, March/April, pp. 22-28, 2010.
-
(2010)
Chip Scale Review, March/April
, pp. 22-28
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Lau, J.H.1
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10
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70349686526
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Study of 15-nm-pitch solder microbumps for 3D IC integration
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A. Yu, J.H. Lau, S. Ho, A. Kumar, Y. Wai, D. Yu, M. Jong, V. Kripesh, D. Pinjala, and D. Kwong, "Study of 15-nm-pitch solder microbumps for 3D IC integration," in IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 6-10.
-
(2009)
IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May
, pp. 6-10
-
-
Yu, A.1
Lau, J.H.2
Ho, S.3
Kumar, A.4
Wai, Y.5
Yu, D.6
Jong, M.7
Kripesh, V.8
Pinjala, D.9
Kwong, D.10
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11
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70349659227
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Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps
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San Diego, CA, May. Also, accepted for publication in IEEE Transactions in Advanced Packaging
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A. Yu, J.H. Lau, S. Ho, A. Kumar, H. Yin, J. Ching, V. Kripesh, D. Pinjala, S. Chen, C. Chan, C. Chao, Ñ. Chiu, M. Huang, and C. Chen, "Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps," in IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 350-354. Also, accepted for publication in IEEE Transactions in Advanced Packaging.
-
(2009)
IEEE Proceedings of Electronic Components and Technology Conference
, pp. 350-354
-
-
Yu, A.1
Lau, J.H.2
Ho, S.3
Kumar, A.4
Yin, H.5
Ching, J.6
Kripesh, V.7
Pinjala, D.8
Chen, S.9
Chan, C.10
Chao, C.11
Chiu, N.12
Huang, M.13
Chen, C.14
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12
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63049114343
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Development of fine pitch solder microbumps for 3D chip stacking
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Also, to be published in IEEE Transactions in Advanced Packaging
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A. Yu, A. Kumar, S. Ho, H. Yin, J.H. Lau, J. Ching, V. Kripesh, D.Pinjala, S. Chen, C. Chan, C. Chao, Ñ. Chiu, M. Huang, and C. Chen, "Development of fine pitch solder microbumps for 3D chip stacking," in IEEE EPTC Proceedings, Singapore, December 2008, pp. 387-392. Also, to be published in IEEE Transactions in Advanced Packaging.
-
(2008)
IEEE EPTC Proceedings, Singapore, December
, pp. 387-392
-
-
Yu, A.1
Kumar, A.2
Ho, S.3
Yin, H.4
Lau, J.H.5
Ching, J.6
Kripesh, V.7
Pinjala, D.8
Chen, S.9
Chan, C.10
Chao, C.11
Chiu, N.12
Huang, M.13
Chen, C.14
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13
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51349088784
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Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package
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A. Yu, N. Khan, and G. Archit, D. Pinjala, K. Toh, V. Kripesh, S. Yoon, and J.H. Lau, "Fabrication of silicon carriers with TSV electrical interconnections and embedded thermal solutions for high power 3-D package," in IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, 2008, pp. 24-28.
-
(2008)
IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL
, pp. 24-28
-
-
Yu, A.1
Khan, N.2
Archit, G.3
Pinjala, D.4
Toh, K.5
Kripesh, V.6
Yoon, S.7
Lau, J.H.8
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14
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70349299917
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Development of silicon carriers with embedded thermal solutions for high power 3-D package
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A. Yu, N. Khan, G. Archit, D. Pinjala, K. Toh, V. Kripesh, S. Yoon, and J.H. Lau, "Development of silicon carriers with embedded thermal solutions for high power 3-D package," IEEE Transactions on Components and Packaging Technology, Vol. 32, No. 3, pp. 566-571, 2009.
-
(2009)
IEEE Transactions on Components and Packaging Technology
, vol.32
, Issue.3
, pp. 566-571
-
-
Yu, A.1
Khan, N.2
Archit, G.3
Pinjala, D.4
Toh, K.5
Kripesh, V.6
Yoon, S.7
Lau, J.H.8
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15
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77949562449
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Integrated liquid cooling systems for 3-D stacked TSV modules
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G. Tang, O. Navas, D. Pinjala, J.H. Lau, A. Yu, and V. Kripesh, "Integrated liquid cooling systems for 3-D stacked TSV modules," IEEE Transactions on Components and Packaging Technologies, Vol. 33, No. 1, pp. 184-195, 2010.
-
(2010)
IEEE Transactions on Components and Packaging Technologies
, vol.33
, Issue.1
, pp. 184-195
-
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Tang, G.1
Navas, O.2
Pinjala, D.3
Lau, J.H.4
Yu, A.5
Kripesh, V.6
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16
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71049162943
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C2W bonding method for MEMS applications
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K. Chen, C. Premachandran, K. Choi, C. Ong, X. Ling, A. Khairyanto, B. Ratmin, P. Myo, and J.H. Lau, "C2W bonding method for MEMS applications," in IEEE Proceedings of Electronics Packaging Technology Conference, 2008, pp. 1283-1287.
-
(2008)
IEEE Proceedings of Electronics Packaging Technology Conference
, pp. 1283-1287
-
-
Chen, K.1
Premachandran, C.2
Choi, K.3
Ong, C.4
Ling, X.5
Khairyanto, A.6
Ratmin, B.7
Myo, P.8
Lau, J.H.9
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17
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51449095637
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A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications
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C.S. Premachandran, J.H. Lau, X. Ling, A. Khairyanto, K. Chen, and E.Myo, "A novel, wafer-level stacking method for low-chip yield and non-uniform, chip-size wafers for MEMS and 3D SIP applications," in IEEE Proceedings of Electronic, Components and Technology Conference, Orlando, FL, 2008, pp. 314-318.
-
(2008)
IEEE Proceedings of Electronic, Components and Technology Conference, Orlando, FL
, pp. 314-318
-
-
Premachandran, C.S.1
Lau, J.H.2
Ling, X.3
Khairyanto, A.4
Chen, K.5
Myo, E.6
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18
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70349658299
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Development of through silicon via (TSV) interposer technology for large die (21 X 21 mm) fine-pitch Cu/low-k FCBGA package
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Also accepted for publication in IEEE Transactions in Advanced Packaging
-
X. Zhang, T. Chai, J.H. Lau, C. Selvanayagam, Ê. Biswas, S. Liu, D. Pinjala, G. Tang, Y. Ong, S. Vempati, E. Wai, H. Li, B. Liao, N. Ranganathan, V. Kripesh, J. Sun, J. Doricko, and C. Vath, "Development of through silicon via (TSV) interposer technology for large die (21 X 21 mm) fine-pitch Cu/low-k FCBGA package," in IEEE Proceedings of Electronic, Components & Technology Conference, San Diego, CA, 2009, pp. 305-312. Also accepted for publication in IEEE Transactions in Advanced Packaging.
-
(2009)
IEEE Proceedings of Electronic, Components & Technology Conference, San Diego, CA
, pp. 305-312
-
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Zhang, X.1
Chai, T.2
Lau, J.H.3
Selvanayagam, C.4
Biswas, E.5
Liu, S.6
Pinjala, D.7
Tang, G.8
Ong, Y.9
Vempati, S.10
Wai, E.11
Li, H.12
Liao, B.13
Ranganathan, N.14
Kripesh, V.15
Sun, J.16
Doricko, J.17
Vath, C.18
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19
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77950959311
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Effect of TSV interposer on the thermal performance of FCBGA package
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G. Hoe, G. Tang, P. Damaruganath, C. Chong, J.H. Lau, X. Zhang, and K. Vaidyanathan, "Effect of TSV interposer on the thermal performance of FCBGA package," in IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore, 2009, pp. 778-786.
-
(2009)
IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore
, pp. 778-786
-
-
Hoe, G.1
Tang, G.2
Damaruganath, P.3
Chong, C.4
Lau, J.H.5
Zhang, X.6
Vaidyanathan, K.7
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20
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70349693680
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Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking
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W.O. Choi, C.S. Premachandran, S. Ong, X. Ling, E. Liao, K. Ahmad, B. Ratmin, K. Chen, P. Thaw, and J.H. Lau, "Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking," in IEEE Proceedings of Electronic, Components & Technology Conference, San Diego, CA, 2009, pp. 333-338.
-
(2009)
IEEE Proceedings of Electronic, Components and Technology Conference, San Diego, CA
, pp. 333-338
-
-
Choi, W.O.1
Premachandran, C.S.2
Ong, S.3
Ling, X.4
Liao, E.5
Ahmad, K.6
Ratmin, B.7
Chen, K.8
Thaw, P.9
Lau, J.H.10
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21
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70349670743
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Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects
-
Also accepted for publication in IEEE Transactions in CPMT
-
S.R. Vempati, S. Nandar, C. Khong, Y. Lim, K. Vaidyanathan, J.H. Lau, B.P. Liew, K.Y. Au, S. Tanary, A. Fenne, R. Erich, and J. Milla, "Development of 3-D silicon die stacked package using flip chip technology with micro bump interconnects," in IEEE Proceedings of Electronic, Components and Technology Conference, San Diego, CA, 2009, pp. 980-987. Also accepted for publication in IEEE Transactions in CPMT.
-
(2009)
IEEE Proceedings of Electronic, Components and Technology Conference, San Diego, CA
, pp. 980-987
-
-
Vempati, S.R.1
Nandar, S.2
Khong, C.3
Lim, Y.4
Vaidyanathan, K.5
Lau, J.H.6
Liew, B.P.7
Au, K.Y.8
Tanary, S.9
Fenne, A.10
Erich, R.11
Milla, J.12
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22
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70349663697
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3D packaging with through silicon via (TSV) for electrical and fluidic interconnections
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N. Khan, L. Yu, P. Tan, S. Ho, N. Su, H. Wai, K. Vaidyanathan, D. Pinjala, J.H. Lau, and T. Chuan, "3D packaging with through silicon via (TSV) for electrical and fluidic interconnections," in IEEE Proceedings of Electronic, Components & Technology Conference, San Diego, CA, 2009, pp. 1153-1 158.
-
(2009)
IEEE Proceedings of Electronic, Components & Technology Conference, San Diego, CA
, pp. 1153-1158
-
-
Khan, N.1
Yu, L.2
Tan, P.3
Ho, S.4
Su, N.5
Wai, H.6
Vaidyanathan, K.7
Pinjala, D.8
Lau, J.H.9
Chuan, T.10
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23
-
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51349133304
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Effect of wafer back grinding on the mechanical behavior of multilayered low-e for 3D-stack packaging applications
-
V.N. Sekhar, S. Lu, A. Kumar, T.C. Chai, V. Lee, S. Wang, X. Zhang, C.S. Premchandran, V. Kripesh, and J.H. Lau, "Effect of wafer back grinding on the mechanical behavior of multilayered low-ê for 3D-stack packaging applications," in IEEE Proceedings of Electronic, Compnents and Technology Conference, Orlando, FL, 2008, pp. 1517-1524.
-
(2008)
IEEE Proceedings of Electronic, Compnents and Technology Conference, Orlando, FL
, pp. 1517-1524
-
-
Sekhar, V.N.1
Lu, S.2
Kumar, A.3
Chai, T.C.4
Lee, V.5
Wang, S.6
Zhang, X.7
Premchandran, C.S.8
Kripesh, V.9
Lau, J.H.10
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24
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51349164996
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Development of 3D silicon module with TSV for wystem in packaging
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N. Khan, V. Rao, S. Lim, S. Ho, V. Lee, X. Zhang, R. Yang, E. Liao, and T. Ranganathan, T. Chai, V. Kripesh, and J.H. Lau, "Development of 3D silicon module with TSV for wystem in packaging," in IEEE Proceed-ings of Electronic, Components and Technology Conference, Orlando, FL, 2008, pp. 550-555.
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(2008)
IEEE Proceed-ings of Electronic, Components and Technology Conference, Orlando, FL
, pp. 550-555
-
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Khan, N.1
Rao, V.2
Lim, S.3
Ho, S.4
Lee, V.5
Zhang, X.6
Yang, R.7
Liao, E.8
Ranganathan, T.9
Chai, T.10
Kripesh, V.11
Lau, J.H.12
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25
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51349094381
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High RF performance TSV for silicon carrier for high frequency application
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S. Ho, S. Yoon, Q. Zhou, K. Pasad, V. Kripesh, and J.H. Lau, "High RF performance TSV for silicon carrier for high frequency application," in IEEE Proceedings of Electronic, Components and Technology Conference, Orlando, FL, 2008, pp. 1956-1952.
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(2008)
IEEE Proceedings of Electronic, Components and Technology Conference, Orlando, FL
, pp. 1956-1952
-
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Ho, S.1
Yoon, S.2
Zhou, Q.3
Pasad, K.4
Kripesh, V.5
Lau, J.H.6
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26
-
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74649084751
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Nonlinear thermal stress/strain analysis of copper filled TSV (through silicon via) and their flip-chip microbumps
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C. Selvanayagam, J.H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, "Nonlinear thermal stress/strain analysis of copper filled TSV (through silicon via) and their flip-chip microbumps," IEEE Transactions on Advanced Packaging, Vol. 32, No. 4, pp. 720-728,2009.
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(2009)
IEEE Transactions on Advanced Packaging
, vol.32
, Issue.4
, pp. 720-728
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Selvanayagam, C.1
Lau, J.H.2
Zhang, X.3
Seah, S.4
Vaidyanathan, K.5
Chai, T.6
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27
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71649088048
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Application of piezoresistive stress sensors in ultra thin device handling and characterization
-
Nov
-
X. Zhang, A. Kumar, Q.X. Zhang, Y.Y. Ong, S.W. Ho, C.H. Khong, V. Kripesh, J.H. Lau, D.-L. Kwong, V. Sundaram, R. Tummula, and M-Geort, "Application of piezoresistive stress sensors in ultra thin device handling and characterization," Journal of Sensors and Actuators: A, Phys-ical, Vol. 156, No. Nov, pp. 2-7, 2009.
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(2009)
Journal of Sensors and Actuators: A, Phys-ical
, Issue.156
, pp. 2-7
-
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Zhang, X.1
Kumar, A.2
Zhang, Q.X.3
Ong, Y.Y.4
Ho, S.W.5
Khong, C.H.6
Kripesh, V.7
Lau, J.H.8
Kwong, D.-L.9
Sundaram, V.10
Tummula, R.11
Geort, M.12
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28
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33845594162
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Novel low cost integration of through chip interconnection and application to CMOS image sensor
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M. Sekiguchi, H. Numata, N. Sato, T. Shirakawa, M. Matsuo, H. Yoshikawa, M. Yanagida, H. Nakayoshi, and K. Takahashi, "Novel low cost integration of through chip interconnection and application to CMOS image sensor," in IEEE Proceedings of Electronic Componen!s and Technology Conference, San Diego, CA, 2006, pp. 1367-1374.
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(2006)
IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA
, pp. 1367-1374
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Sekiguchi, M.1
Numata, H.2
Sato, N.3
Shirakawa, T.4
Matsuo, M.5
Yoshikawa, H.6
Yanagida, M.7
Nakayoshi, H.8
Takahashi, K.9
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30
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70449474060
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New York, John Wiley
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P. Garrou, C. Bower, and P. Ramm, "3D Integration: Technology and Applications," New York, John Wiley, 2009.
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(2009)
3D Integration: Technology and Applications
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Garrou, P.1
Bower, C.2
Ramm, P.3
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31
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51349132537
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Through silicon via technology-Processes and reliability for wafer-level 3D system integration
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P. Ramm, M. Wolf, A. Klumpp, R. Wieland, A. Wunderle, A. Michel, and H. Reichl, "Through silicon via technology-Processes and reliability for wafer-level 3D system integration," in Proceedings of the IEEE ECTC, Orlando, FL, 2008, pp. 847-852.
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(2008)
Proceedings of the IEEE ECTC, Orlando, FL
, pp. 847-852
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Ramm, P.1
Wolf, M.2
Klumpp, A.3
Wieland, R.4
Wunderle, A.5
Michel, A.6
Reichl, H.7
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32
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61649092607
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Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
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P.S. Andry, C.K. Tsang, B.C. Webb, E.J. Sprogis, S.L. Wright, B. Bang, and D.G. Manzer, "Fabrication and characterization of robust through-silicon vias for silicon-carrier applications," IBM Journal of Research and Development, Vol. 52, No. 6, pp. 571-581, 2008.
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(2008)
IBM Journal of Research and Development
, vol.52
, Issue.6
, pp. 571-581
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Andry, P.S.1
Tsang, C.K.2
Webb, B.C.3
Sprogis, E.J.4
Wright, S.L.5
Bang, B.6
Manzer, D.G.7
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33
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51349137210
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3-D silicon integration
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J.U. Knickerbocker, P.S. Andry, B. Dang, R.R. Horton, C S. Patel, R.J. Polastre, K. Sakuma, E.S. Sprogis, C.K. Tsang, B.C. Webb, and S.L. Wright "3-D silicon integration," in IEEE Proceedings of Electronic Components and Technology Conference, 2008, pp. 538-543.
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(2008)
IEEE Proceedings of Electronic Components and Technology Conference
, pp. 538-543
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Knickerbocker, J.U.1
Andry, P.S.2
Dang, B.3
Horton, R.R.4
Patel, C.S.5
Polastre, R.J.6
Sakuma, K.7
Sprogis, E.S.8
Tsang, C.K.9
Webb, B.C.10
Wright, S.L.11
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34
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51349119303
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A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection
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K. Kumagai, Y. Yoneda, H. Izumino, H. Shimojo, M. Sunohara, T. Kurihara, "A silicon interposer BGA package with Cu-filled TSV and multi-layer Cu-plating interconnection," in IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, 2008, pp. 571-576.
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(2008)
IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL
, pp. 571-576
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Kumagai, K.1
Yoneda, Y.2
Izumino, H.3
Shimojo, H.4
Sunohara, M.5
Kurihara, T.6
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35
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51349111449
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Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring
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M. Sunohara, T. Tokunaga, T. Kurihara, M. Higashi, "Silicon interposer with TSVs (through silicon vias) and fine multilayer wiring," in IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL, 2008, pp. 847-852.
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(2008)
IEEE Proceedings of Electronic Components and Technology Conference, Orlando, FL
, pp. 847-852
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Sunohara, M.1
Tokunaga, T.2
Kurihara, T.3
Higashi, M.4
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36
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35348877852
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Power delivery network design for 3D SIP integrated over silicon interposer platform
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H.S. Lee, Y-S. Choi, E. Song, K. Choi, T. Cho, S. Kang, "Power delivery network design for 3D SIP integrated over silicon interposer platform," in IEEE Proceedings of Electronic Components and Technology Conference, Reno, NV, 2007, pp. 1193-1198.
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(2007)
IEEE Proceedings of Electronic Components and Technology Conference, Reno, NV
, pp. 1193-1198
-
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Lee, H.S.1
Choi, Y.-S.2
Song, E.3
Choi, K.4
Cho, T.5
Kang, S.6
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37
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0034483014
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Silicon interposer technology for high-density package
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M. Matsuo, N. Hayasaka, K. Okumura, "Silicon interposer technology for high-density package," In IEEE Proceedings of Electronic Components and Technology Conference, Las Vegas, NV, 2000, pp. 1455-1459.
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(2000)
IEEE Proceedings of Electronic Components and Technology Conference, Las Vegas, NV
, pp. 1455-1459
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Matsuo, M.1
Hayasaka, N.2
Okumura, K.3
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38
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33845581077
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Effective thermal via and decoupling capacitor insertion for 3D system-on-package
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E. Wong, J. Minz, and S.K. Lim, "Effective thermal via and decoupling capacitor insertion for 3D system-on-package," in IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA, 2006, pp. 1795-1801.
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(2006)
IEEE Proceedings of Electronic Components and Technology Conference, San Diego, CA
, pp. 1795-1801
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Wong, E.1
Minz, J.2
Lim, S.K.3
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39
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51349090206
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