Novel thinning/backside passivation for substrate coupling depression of 3D IC

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1395-1399

  Kwon, Woonseong ^a   Lee, Jaesik ^a   Lee, Vincent ^a   Seetoh, Justin ^a   Yeo, Yenchen ^a   Khoo, Yeemong ^a   Ranganathan, Nagarajan ^a   Teo, Keng Hwa ^a   Gao, Shan ^a  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; BUILDING BLOCKES; CMP PROCESS; COPPER CONTAMINATION; CRUCIAL TECHNOLOGY; ETCHBACK PROCESS; HEIGHT VARIATION; INSULATION LAYERS; INTEGRATION TECHNOLOGIES; LOW TEMPERATURES; NONUNIFORMITY; PROCESS DEFECTS; PROCESS INTEGRATION; SUBSTRATE COUPLINGS; THICK DIELECTRICS; THIN WAFERS; THINNING PROCESS; TOTAL THICKNESS VARIATIONS; WAFER THINNING;

DIELECTRIC MATERIALS; INSULATION; PLASMA ETCHING; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; TECHNOLOGY; THREE DIMENSIONAL;

PASSIVATION;

EID: 79960415070     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898694     Document Type: Conference Paper

References (5)

1. K. Puttaswamy and G. H. Loh, "Implementing Caches in a 3D Technology for High Performance Processors", Proceedings of the IEEE International Conference on Computer Design, San Jose, CA, 2005, pp. 525-532.
2. J. Burns et al., "Three-dimensional integrated circuits for low-power, high-bandwidth systems on a chip", in IEEE ISSCC Dig. Tech. Papers, 2001, pp. 268-269.
3. W. R. Davis et al., "Demystifying 3-D ICs: The pros and cons of going vertical", IEEE Design & Test of Computers, vol. 22, no. 6, pp. 498-510, Nov./Dec. 2005.
4. M. Rousseau et al., "Through-silicon via based 3D IC technology: electrostatic simulations for design methodology", Proceedings of the 2008 IMAPS Device Packaging Conference, Phoenix, Arizona, March 17-20, 2008.
5. Bradby, J. E. et al, "Mechanical deformation in silicon by micro-indentation", J. Mater. Res., Vol. 16, No. 5, May 2001, pp. 1500-1507.