Fabrication and characterization of robust through-silicon vias for silicon-carrier applications

IBM Journal of Research and Development

Volumn 52, Issue 6, 2008, Pages 571-581

  Andry, Paul S ^a   Tsang, Cornelia K ^a   Webb, Bucknell C ^a   Sprogis, Edmund J ^b   Wright, Steven L ^a   Dang, Bing ^a   Manzer, Dennis G ^a  

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ELECTRONICS PACKAGING; INTEGRATED CIRCUIT INTERCONNECTS; RESEARCH LABORATORIES; SILICON; SILICON WAFERS;

ELECTRICAL AND MECHANICAL PROPERTIES; ENABLING TECHNOLOGIES; FABRICATION AND CHARACTERIZATIONS; INTEGRATED CIRCUITS (ICS); LABORATORY ENVIRONMENT; SOLDER INTERCONNECTIONS; THROUGH SILICON VIAS; VERTICAL INTERCONNECTIONS;

THREE DIMENSIONAL INTEGRATED CIRCUITS;

EID: 61649092607     PISSN: 00188646     EISSN: 00188646     Source Type: Journal    
DOI: 10.1147/JRD.2008.5388558     Document Type: Article

References (8)

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