Design, assembly and reliability of large die and fine-pitch Cu/low-k flip chip package

Microelectronics Reliability

Volumn 50, Issue 7, 2010, Pages 986-994

  Ong, Yue Ying ^a   Ho, Soon Wee ^a   Vaidyanathan, Kripesh ^a   Sekhar, Vasarla Nagendra ^a   Jong, Ming Chinq ^a   Yak Long, Samuel Lim ^a   Wen Sheng, Vincent Lee ^a   Wai, Leong Ching ^a   Rao, Vempati Srinivasa ^a   Ong, Jimmy ^b   Ong, Xuefen ^c   Zhang, Xiaowu ^a   Seung, Yoon Uk ^a   Lau, John H ^a   Lim, Yeow Kheng ^d   Yeo, David ^d   Chan, Kai Chong ^d   Yanfeng, Zhang ^d   Tan, Juan Boon ^d   Sohn, Dong Kyun ^d  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b NATIONAL UNIVERSITY OF SINGAPORE   (Singapore)

^c NANYANG TECHNOLOGICAL UNIVERSITY   (Singapore)

^d CHARTERED SEMICONDUCTOR MANUFACTURING LTD   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

65-NM NODE; BUMP PITCHES; CU/LOW-K FLIP CHIP; DEVICE ENGINEERING; FLIP CHIP ASSEMBLIES; FLIP-CHIP PACKAGES; FLIP-CHIP PACKAGING; K-GENERATION; LEAD SOLDERS; LEAD-FREE; LEVEL 2; MOISTURE SENSITIVITY; REDISTRIBUTION LAYERS; RELIABILITY ASSESSMENTS; RELIABILITY PERFORMANCE; SOLDER ALLOYS; SOLDER BUMP; TEST VEHICLE; UNDERFILL MATERIALS;

DIES; ELECTRONIC EQUIPMENT MANUFACTURE; FLIP CHIP DEVICES; LEAD; PACKAGING; RELIABILITY ANALYSIS; SILVER; SOLDERING;

CHIP SCALE PACKAGES;

EID: 77955709131     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/j.microrel.2010.03.010     Document Type: Conference Paper

References (16)

1. Y. Takao, H. Kudo, J. Mitani, Y. Kotani, S. Yamaguchi, and K. Yoshie A 0.11 μm CMOS technology featuring copper and very low k interconnects with high performance and reliability Microelectron Reliab 42 2002 15 25
2. S. Chungpaoboonpatana, and F.G. Shi Advanced HiCTE flip chip packaging of 90-nm Cu/low-k Chips: underfill novel terminal pad structures and processing optimization J Electron Mater 34 7 2005 977 993
3. G. Wang, C. Merrill, J.-H. Zhao, S.K. Groothuis, and P.S. Ho Packaging effects on reliability of Cu/low-k interconnects IEEE Trans Dev Mater Reliab 3 4 2003 119 128
4. G. Wang, P.S. Ho, and S. Groothuis Chip-packaging interaction: a critical concern for Cu/low-k packaging Microelectron Reliab 45 2005 1079 1093
5. S.W. Yoon, M.L. Thew, Y.L. Lim, W.Y. Hnin, T.C. Chai, and A.G.K. Viswanath 150 μm pitch Cu/low-k flip chip packaging with polymer encapsulated dicing line (PEDL) and Cu column interconnects IEEE Trans Adv Packag 31 1 2008 58 65
6. F.X. Che, X. Zhang, W.H. Zhu, and T.C. Chai Reliability evaluation for copper/low-k structures based on experimental and numerical methods IEEE Trans Dev Mater Reliab 8 3 2008 455 463
7. Biswas K, Liu S, Zhang X, Chai T.C. Thermo-mechanical design of large die fine pitch copper/low-k FCBGA and lead-free interconnections. In: Proceedings of electronic packaging and high density packaging conference; 2008.
8. Ong J, Zhang X, Kripesh V, Lim Y.K, Yeo D, Chan K.C, et al. Structural design and optimization of 65 nm Cu/low-k flip chip package. In: Proceedings of electronics packaging technology conference; 2007. p. 488-92.
9. Fiori V, Gallois-Garreignot S, Tavernier C, Jaouen H, Juge A. Chip-package interactions: some combined package effects on copper/low-k interconnect delaminations. In: Proceedings of 2nd electronics system integration technology conference. p. 713-8.
10. W.D. van Driel Facing the challenge of designing for Cu/low-k reliability Microelectron Reliab 47 2007 1969 1974
11. Ong X.F, Ho S.W, Ong Y.Y, Wai L.C, Kripesh V, Lim Y.K, et al. A systematic methodology for fine pitch Cu/Low-k FCBGA package. In: Proceedings of electronics packaging technology conference; 2007. p. 646-51.
12. IPC/JEDEC-J-STD-020, Moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices, Joint industry standard.
13. JESD22-A104C. Temperature cycling, JEDEC standard; 2005.
14. JESD22-A118. Accelerated moisture resistance-unbiased HAST, JEDEC Standard; 2000.
15. Libres J, Robinson K. Challenges in the assembly of large die high bump density Pb-free flip chip packages, International electronics manufacturing technology symposium; 2007. p. 346-52.
16. V. Wakharkar, C. Matayabas, E. Lehman, R. Manepalli, M. Renavikar, and S. Jayaraman Materials technologies for thermomechanical management of organic packages Intel Technol J 9 04 2005 310 324