Development of large die fine-pitch Cu/low-κ; FCBGA package with through silicon via (TSV) interposer

IEEE Transactions on Components, Packaging and Manufacturing Technology

Volumn 1, Issue 5, 2011, Pages 660-672

  Chai, Tai Chong ^a   Zhang, Xiaowu ^a   Lau, John H ^b   Selvanayagam, Cheryl S ^a   Damaruganath, Pinjala ^a   Hoe, Yen Yi Germaine ^a   Ong, Yue Ying ^a   Rao, Vempati Srinivas ^a   Wai, Eva ^a   Li, Hong Yu ^a   Bin Liao, E ^a   Ranganathan, Nagarajan ^a   Vaidyanathan, Kripesh ^a   Liu, Shiguo ^c   Sun, Jiangyan ^d   Ravi, Mullapudi ^e   Vath, Charles J ^f   Tsutsumi, Yoshihiro ^g  

^a INSTITUTE OF MICROELECTRONICS   (Singapore)

^b INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^c IBIDEN Singapore Pte Ltd   (Singapore)

^d Shanghai Sinyang Semiconductor Materials Co Ltd   (China)

^e Tango Systems Inc   (United States)

^f ASM Technology Singapore Pte Ltd   (Singapore)

^g DISCO Hi Tec Pte Ltd   (Singapore)

Author keywords

Cu low chip; mechanical modeling; packaging assembly; reliability; thermal modeling; through silicon via interposer; wafer fabrication

Indexed keywords

MECHANICAL MODELING; PACKAGING ASSEMBLIES; THERMAL MODELING; THROUGH-SILICON-VIA; WAFER FABRICATIONS;

COMPUTER SIMULATION; LEAD; METAL TESTING; RELIABILITY; SILICON WAFERS; STRESSES; SUBSTRATES; THERMOANALYSIS;

CHIP SCALE PACKAGES;

EID: 84856460079     PISSN: 21563950     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCPMT.2010.2101911     Document Type: Article

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