메뉴 건너뛰기




Volumn , Issue , 2011, Pages 1815-1821

Characterization of thermo-mechanical stress and reliability issues for Cu-filled TSVs

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; CROSS SECTION; DIELECTRIC LAYER; ELECTRON BACK-SCATTERED DIFFRACTION; ELEVATED TEMPERATURE; GRAIN SIZE; HIGH QUALITY; NONDESTRUCTIVE ANALYSIS; THERMO-MECHANICAL; THERMO-MECHANICAL STRESS; THROUGH SILICON VIAS; WAFER LEVEL PACKAGING; XRAY IMAGING;

EID: 79960402759     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898761     Document Type: Conference Paper
Times cited : (38)

References (17)
  • 5
    • 46049085227 scopus 로고    scopus 로고
    • High density 3-D integration technology for massively parallel signal processing in advanced infrared focal plane array sensors
    • San Francisco, CA, Dec. 2006; published in IEDM Technical Digest, Dec
    • D. Temple, et al., "High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors", 52nd IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 2006; published in IEDM Technical Digest, Dec. 2006, pp. 1-4.
    • (2006) 52nd IEEE International Electron Devices Meeting , pp. 1-4
    • Temple, D.1
  • 6
    • 61649092607 scopus 로고    scopus 로고
    • Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
    • Nov
    • P. S. Andry, et al., "Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications", IBM Journal of Research and Development, Vol. 52, No. 6, pp. 571-581, Nov. 2008.
    • (2008) IBM Journal of Research and Development , vol.52 , Issue.6 , pp. 571-581
    • Andry, P.S.1
  • 7
    • 78651469386 scopus 로고    scopus 로고
    • Electrical demonstration of TSV interconnects and multilevel metallization for 3D Si interposer applications
    • Research Triangle Park, NC, Nov
    • E. Vick, S. Goodwin, and D. Temple, "Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications", IMAPS 2010-43rd International Symposium on Microelectronics, Research Triangle Park, NC, Nov. 2010, pp. 7-14.
    • (2010) IMAPS 2010-43rd International Symposium on Microelectronics , pp. 7-14
    • Vick, E.1    Goodwin, S.2    Temple, D.3
  • 10
    • 77955209967 scopus 로고    scopus 로고
    • Enabling 10μm pitch hybrid Cu-Cu IC stacking with through silicon vias
    • Las Vegas, NV, May
    • C. Huyghebaert, et al., "Enabling 10μm Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1083-1087.
    • (2010) Proc. of 60th Electronic Components and Technology Conference , pp. 1083-1087
    • Huyghebaert, C.1
  • 11
    • 77955214215 scopus 로고    scopus 로고
    • TSV plating technologies
    • Seoul, Korea, Jan
    • Y. Zhang, et al., "TSV Plating Technologies", Semicon Korea 2009, Seoul, Korea, Jan. 2009.
    • (2009) Semicon Korea 2009
    • Zhang, Y.1
  • 15
    • 70349655245 scopus 로고    scopus 로고
    • Optimization of chemistry and process parameters for void-free copper electroplating of high aspect ratio through-silicon vias for 3D integration
    • San Diego, CA, May
    • D. Malta, C. Gregory, D. Temple, C. Wang, T. Richardson, and Y. Zhang, "Optimization of Chemistry and Process Parameters for Void-Free Copper Electroplating of High Aspect Ratio Through-Silicon Vias for 3D Integration", Proc. of 59th Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 1301-1306.
    • (2009) Proc. of 59th Electronic Components and Technology Conference , pp. 1301-1306
    • Malta, D.1    Gregory, C.2    Temple, D.3    Wang, C.4    Richardson, T.5    Zhang, Y.6
  • 16
    • 77955220951 scopus 로고    scopus 로고
    • Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects
    • Las Vegas, NV, May
    • D. Malta, et al., "Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1769-1775.
    • (2010) Proc. of 60th Electronic Components and Technology Conference , pp. 1769-1775
    • Malta, D.1
  • 17
    • 77955210503 scopus 로고    scopus 로고
    • Micro structure analysis for system in package components? Novel tools for fault isolation, target preparation, and high-resolution material diagnostics
    • Las Vegas, NV, May
    • M. Petzold, et al., "Micro Structure Analysis for System in Package Components? Novel Tools for Fault Isolation, Target Preparation, and High-Resolution Material Diagnostics", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1296-1302.
    • (2010) Proc. of 60th Electronic Components and Technology Conference , pp. 1296-1302
    • Petzold, M.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.