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1
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34249801921
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3D system integration technologies
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Hsinchu, Taiwan, April
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E. Beyne, "3D System Integration Technologies", 2006 International Symposium on VLIS Technology, Systems, and Applications, Hsinchu, Taiwan, April 2006, pp. 1-9.
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(2006)
2006 International Symposium on VLIS Technology, Systems, and Applications
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Beyne, E.1
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2
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51349137210
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3D silicon integration
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Lake Buena Vista, FL, May
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J. Knickerbocker, et al., "3D Silicon Integration", Proc. of 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, May 2008, pp. 538-543.
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Proc. of 58th Electronic Components and Technology Conference
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Knickerbocker, J.1
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4
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70349672000
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3-DICs & TSV, A market analysis
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Burlingame, CA, Nov
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J. Eloy, "3-DICs & TSV, A Market Analysis", 5th Annual 3D Architectures for Semiconductor Integration and Packaging Conference, Burlingame, CA, Nov. 2008.
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(2008)
5th Annual 3D Architectures for Semiconductor Integration and Packaging Conference
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Eloy, J.1
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5
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46049085227
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High density 3-D integration technology for massively parallel signal processing in advanced infrared focal plane array sensors
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San Francisco, CA, Dec. 2006; published in IEDM Technical Digest, Dec
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D. Temple, et al., "High Density 3-D Integration Technology for Massively Parallel Signal Processing in Advanced Infrared Focal Plane Array Sensors", 52nd IEEE International Electron Devices Meeting, San Francisco, CA, Dec. 2006; published in IEDM Technical Digest, Dec. 2006, pp. 1-4.
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(2006)
52nd IEEE International Electron Devices Meeting
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Temple, D.1
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6
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61649092607
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Fabrication and characterization of robust through-silicon vias for silicon-carrier applications
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Nov
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P. S. Andry, et al., "Fabrication and Characterization of Robust Through-Silicon Vias for Silicon-Carrier Applications", IBM Journal of Research and Development, Vol. 52, No. 6, pp. 571-581, Nov. 2008.
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IBM Journal of Research and Development
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Andry, P.S.1
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7
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78651469386
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Electrical demonstration of TSV interconnects and multilevel metallization for 3D Si interposer applications
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Research Triangle Park, NC, Nov
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E. Vick, S. Goodwin, and D. Temple, "Electrical Demonstration of TSV Interconnects and Multilevel Metallization for 3D Si Interposer Applications", IMAPS 2010-43rd International Symposium on Microelectronics, Research Triangle Park, NC, Nov. 2010, pp. 7-14.
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(2010)
IMAPS 2010-43rd International Symposium on Microelectronics
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Vick, E.1
Goodwin, S.2
Temple, D.3
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10
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77955209967
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Enabling 10μm pitch hybrid Cu-Cu IC stacking with through silicon vias
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Las Vegas, NV, May
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C. Huyghebaert, et al., "Enabling 10μm Pitch Hybrid Cu-Cu IC Stacking with Through Silicon Vias", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1083-1087.
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Proc. of 60th Electronic Components and Technology Conference
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Huyghebaert, C.1
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11
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77955214215
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TSV plating technologies
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Seoul, Korea, Jan
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Y. Zhang, et al., "TSV Plating Technologies", Semicon Korea 2009, Seoul, Korea, Jan. 2009.
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(2009)
Semicon Korea 2009
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Zhang, Y.1
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12
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51349090206
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Through silicon via copper electrodeposition for 3D integration
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Lake Buena Vista, FL, May
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R. Beica, C. Sharbono, T. Ritzdorf, "Through Silicon Via Copper Electrodeposition for 3D Integration", Proc. of 58th Electronic Components and Technology Conference, Lake Buena Vista, FL, May 2008, pp. 577-583.
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(2008)
Proc. of 58th Electronic Components and Technology Conference
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Beica, R.1
Sharbono, C.2
Ritzdorf, T.3
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13
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79960426100
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Nondestructive characterization of through silicon vias (TSVs)
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Santa Clara, Ca, Oct
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M. Weatherspoon, D. Nicol, and J. Miller, "Nondestructive Characterization of Through Silicon Vias (TSVs)", International Wafer Level Packaging Conference (IWLPC), Santa Clara, Ca, Oct. 2009.
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(2009)
International Wafer Level Packaging Conference (IWLPC)
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Weatherspoon, M.1
Nicol, D.2
Miller, J.3
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14
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70349694995
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MICROFAB DVF 200: A fast, robust, electrochemical process for thru silicon vias applications
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AZ, March
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Thomas B. Richardson, et al., "MICROFAB DVF 200: A Fast, Robust, Electrochemical Process for Thru Silicon Vias Applications", Proc. of IMAPS 4th International Conference and Exhibition on Device Packaging, Scottsdale, AZ, March 2008, pp. 119-123.
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Proc. of IMAPS 4th International Conference and Exhibition on Device Packaging, Scottsdale
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Richardson, T.B.1
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15
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70349655245
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Optimization of chemistry and process parameters for void-free copper electroplating of high aspect ratio through-silicon vias for 3D integration
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San Diego, CA, May
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D. Malta, C. Gregory, D. Temple, C. Wang, T. Richardson, and Y. Zhang, "Optimization of Chemistry and Process Parameters for Void-Free Copper Electroplating of High Aspect Ratio Through-Silicon Vias for 3D Integration", Proc. of 59th Electronic Components and Technology Conference, San Diego, CA, May 2009, pp. 1301-1306.
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(2009)
Proc. of 59th Electronic Components and Technology Conference
, pp. 1301-1306
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Malta, D.1
Gregory, C.2
Temple, D.3
Wang, C.4
Richardson, T.5
Zhang, Y.6
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16
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77955220951
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Integrated process for defect-free copper plating and chemical-mechanical polishing of through-silicon vias for 3D interconnects
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Las Vegas, NV, May
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D. Malta, et al., "Integrated Process for Defect-Free Copper Plating and Chemical-Mechanical Polishing of Through-Silicon Vias for 3D Interconnects", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1769-1775.
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(2010)
Proc. of 60th Electronic Components and Technology Conference
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Malta, D.1
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17
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77955210503
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Micro structure analysis for system in package components? Novel tools for fault isolation, target preparation, and high-resolution material diagnostics
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Las Vegas, NV, May
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M. Petzold, et al., "Micro Structure Analysis for System in Package Components? Novel Tools for Fault Isolation, Target Preparation, and High-Resolution Material Diagnostics", Proc. of 60th Electronic Components and Technology Conference, Las Vegas, NV, May 2010, pp. 1296-1302.
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(2010)
Proc. of 60th Electronic Components and Technology Conference
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Petzold, M.1
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