-
2
-
-
28344445261
-
Predicting the performance of a 3D processor-memory stack
-
P. Jacob, et al., "Predicting the Performance of a 3D Processor-memory Stack", IEEE Design and Test of Computers, vol. 22, pp. 540-547, 2005.
-
(2005)
IEEE Design and Test of Computers
, vol.22
, pp. 540-547
-
-
Jacob, P.1
-
3
-
-
70549107724
-
Impact of die-to-die and within-die parameter variations on the clock frequency and throughput of multi-core processors
-
K. A. Bowman, et al., "Impact of Die-to-Die and Within-Die Parameter Variations on the Clock Frequency and Throughput of Multi-Core Processors", IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 17, no. 12, 2009.
-
(2009)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, vol.17
, Issue.12
-
-
Bowman, K.A.1
-
4
-
-
61649087224
-
Is 3D chip technology the next growth engine for performance improvement?
-
P. G. Emma, et al., "Is 3D Chip Technology the Next Growth Engine for Performance Improvement?", IBM J. Res. & Dev. vol. 52, no. 6, pp. 541-552, 2008.
-
(2008)
IBM J. Res. & Dev.
, vol.52
, Issue.6
, pp. 541-552
-
-
Emma, P.G.1
-
5
-
-
67649202573
-
Optical interconnects for board level applications
-
R. Dangel, et al., "Optical Interconnects for Board Level Applications", Proc. of SPIE vol. 7219, pp. 1-7, 2009.
-
(2009)
Proc. of SPIE
, vol.7219
, pp. 1-7
-
-
Dangel, R.1
-
6
-
-
1942468606
-
Optical and electrical interconnect partition length based on chip-to-chip bandwidth maximization
-
A. Naeemi, et al., "Optical and Electrical Interconnect Partition Length Based on Chip-to-Chip Bandwidth Maximization", IEEE Photonics Technology Letters, vol. 16, no. 4, pp. 1221-1223, 2004.
-
(2004)
IEEE Photonics Technology Letters
, vol.16
, Issue.4
, pp. 1221-1223
-
-
Naeemi, A.1
-
9
-
-
42149098650
-
Comparison of bandwidth limits for on-card electrical and optical interconnects for 100 Gb/s and beyond
-
P. Pepeljugosk, et al., "Comparison of Bandwidth Limits for On-Card Electrical and Optical Interconnects for 100 Gb/s and Beyond", Proc. SPIE vol. 6897, pp. 1-7, 2008.
-
(2008)
Proc. SPIE
, vol.6897
, pp. 1-7
-
-
Pepeljugosk, P.1
-
11
-
-
79960428792
-
Impact of near surface thermal stresses on interfacial reliability of through-silicon-vias for 3-D interconnects
-
S. Ryu, et al., "Impact of Near Surface Thermal Stresses on Interfacial Reliability of Through-Silicon-Vias for 3-D Interconnects", IEEE Transactions on Device and Materials Relaibility, vol. PP, issue. 99, 2010.
-
(2010)
IEEE Transactions on Device and Materials Relaibility
, Issue.99
-
-
Ryu, S.1
-
13
-
-
79960403499
-
Optoelectronic package having optical waveguide hole and 4-ch × 10-Gb/s Chip-to-chip interconnection using thin-film waveguide connector
-
R&D Center, NGK Spark Plug Co., Ltd
-
Yutaka Takagi, et al., R&D Center, NGK Spark Plug Co., Ltd. "Optoelectronic Package having Optical Waveguide Hole and 4-ch × 10-Gb/s Chip-to-Chip Interconnection using Thin-film Waveguide Connector", IEEE Conference on Optical Fiber Communication, pp. 1-3, 2009.
-
(2009)
IEEE Conference on Optical Fiber Communication
, pp. 1-3
-
-
Takagi, Y.1
-
14
-
-
66749093535
-
Optical connection between optical via hole in BGA package and optical waveguide on board
-
Kyocera Corporation
-
Keiko ODA, et al., Kyocera Corporation "Optical Connection between Optical Via Hole in BGA Package and Optical Waveguide on Board", IEICE Transactions on Electronics, vol. E92. C, issue 2, pp. 239-246, 2009.
-
(2009)
IEICE Transactions on Electronics
, vol.E92 C
, Issue.2
, pp. 239-246
-
-
Keiko, O.D.A.1
-
17
-
-
79953896186
-
Wafer level batch fabrication of silicon microchannel heat sink and electrical through-silicon vias for 3D ICs
-
J. Zaveri, et al., "Wafer Level Batch Fabrication of Silicon Microchannel Heat Sink and Electrical Through-Silicon Vias for 3D ICs", IMAPS 42nd International Symposium on Microelectronics, 2009.
-
(2009)
IMAPS 42nd International Symposium on Microelectronics
-
-
Zaveri, J.1
-
18
-
-
70349675218
-
Failure mechanisms and optimum design for electroplated copper through-silicon vias
-
Xi Liu, et al., "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias", Proc. 59th Electronic Components and Technology Conf., pp. 624-629, 2009.
-
(2009)
Proc. 59th Electronic Components and Technology Conf.
, pp. 624-629
-
-
Liu, X.1
-
19
-
-
77950251592
-
A 'Mesh' seed layer for improved through-silicon-via fabrication
-
J. Lai, et al., "A 'Mesh' Seed Layer for Improved Through-Silicon-Via Fabrication", Journal of Micromechanics and Microenineering, vol. 2, pp. 1-6, 2010.
-
(2010)
Journal of Micromechanics and Microenineering
, vol.2
, pp. 1-6
-
-
Lai, J.1
-
20
-
-
2142782206
-
Fabrication of polymeric multimode waveguides and devices in SU-8 photoresist using selective polymerization
-
A. Borreman, et al., "Fabrication of Polymeric Multimode Waveguides and Devices in SU-8 Photoresist Using Selective Polymerization", Proc. Symposium IEEE/LEOS Benelux Chapter, pp. 83-86, 2002.
-
(2002)
Proc. Symposium IEEE/LEOS Benelux Chapter
, pp. 83-86
-
-
Borreman, A.1
-
22
-
-
49349094572
-
300-Gb/s, 24-channel full-duplex, 850-nm, CMOS-based optical transceivers
-
C. L. Schow, et al., "300-Gb/s, 24-Channel Full-Duplex, 850-nm, CMOS-Based Optical Transceivers", Optical Fiber communication/National Fiber Optic Engineers Conference, pp. 1-3, 2008.
-
(2008)
Optical Fiber Communication/National Fiber Optic Engineers Conference
, pp. 1-3
-
-
Schow, C.L.1
-
24
-
-
31644448596
-
-
IEEE Electron Device Letters
-
B. Dang, et al., "Integrated thermal-fluidic I/O interconnects for an on-chip microchannel heat sink", IEEE Electron Device Letters, vol. 27, no. 2, pp. 117-119, 2006.
-
(2006)
Integrated Thermal-fluidic I/O Interconnects for an On-chip Microchannel Heat Sink
, vol.27
, Issue.2
, pp. 117-119
-
-
Dang, B.1
|