Low-cost TSV process using electroless Ni plating for 3D stacked DRAM

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1094-1099

  Kawano, Masaya ^a   Takahashi, Nobuaki ^a   Komuro, Masahiro ^a   Matsui, Satoshi ^a  

^a RENESAS TECHNOLOGY CORP   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

ADDITIONAL COSTS; ELECTROLESS; ELECTROLESS NI PLATING; ELECTROLESS NICKEL; FABRICATION PROCESS; POLY-SI; SCALE INTEGRATED CIRCUITS; STACKED DYNAMIC RANDOM ACCESS MEMORIES; THREE DIMENSIONAL INTEGRATION; THROUGH SILICON VIAS;

FABRICATION; GOLD PLATING; PALLADIUM; POLYSILICON; THREE DIMENSIONAL;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 77955180540     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490838     Document Type: Conference Paper

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