A thermal performance measurement method for blind through silicon vias (TSVs) in a 300mm wafer

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1204-1210

  Chien, Heng Chieh ^a   Chao, Yu Lin ^a   Lau, John H ^a   Tain, Ra Min ^a   Dai, Ming Ji ^a   Tzeng, Pei Jer ^a   Lin, Cha Hsin ^a   Hsin, Yu Chen ^a   Chen, Shang Chun ^a   Chen, Jui Chin ^a   Chen, Chien Chou ^a   Ho, Chi Hon ^a   Lo, Wei Chung ^a   Ku, Tzu Kun ^a   Kao, Ming Jer ^a  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

300-MM SILICON WAFERS; 300MM WAFER; A-THERMAL; MEASURED RESULTS; MEASUREMENT METHODS; MEASUREMENT TIME; MEASURING TECHNIQUE; SIMULATION RESULT; THROUGH SILICON VIAS; WAFER THINNING;

SILICON WAFERS; TESTING;

SEMICONDUCTING SILICON COMPOUNDS;

EID: 79960428427     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898663     Document Type: Conference Paper

References (12)

1. J. U. Kinckerbocker, P. S. Andry, B. Dang et al, "Three-dimensional silicon integration", IBM J. Res. & Dev., Vol. 52, No. 6 (2008), pp. 553-569.
2. John H. Lau, Reliability of RoHS-Compliant 2D and 3D IC Interconnects, McGraw-Hill (New York, 2010)
3. John H. Lau, C. K. Lee, C. S. Premachandran, Yu Aibin, Advanced MEMS Packaging, McGraw-Hill (New York, 2009)
4. M. Koyanagi, H. Kurino, T. Matsumoto et al, "New three dimensional integration technology for future system-on silicon LSIs", Proc. IEEE Int. Workshop Chip Package Co-Design, 1998, pp. 96-103.
5. M. Koyanagi, H. Kurino, K. W. Lee et al, "Future systemon-silicon LSI chips", IEEE Micro, vol. 18, No. 4, (1998), pp. 17-22.
6. H. Kurino, K. W. Lee, T. Nakamura et al, "Intelligent image sensor chip with three dimensional structure", IEEE IEDM Tech. Dig., 1999, pp. 879-882.
7. K. W. Lee, T. Nakamura, T. Ono, Y. Yamada et al, "Three-dimensional shared memory fabricated using wafer stacking technology", IEEE IEDM Tech. Dig., 2000, pp. 165-168.
8. T. Ono, T. Mizukusa, T. Nakamura et al, "Three-dimensional processor system fabricating by wafer stacking technology", Proc. Int. Symp. Low-Power High-Speed Chips, 2002, pp. 186-193.
9. M. Motoyoshi, K. Kamibayashi, M. Bonkohara, and M. Koyanagi, "3D-LSI and its key supporting technologies", Tech. Dig. 3D Architect. Semiconduct. Integr. Packag., Nov. 2006.
10. M. Koyanagi, T. Nakamura, Y. Yamada et al, "Three-dimensional integration technology based on wafer bonding with vertical buried interconnections", IEEE Trans. Electron Devices, vol. 53, (2006), pp. 2799-2808.
11. Wu, L., Wang, Yu-Po, Kee, S. C., Wallace, et al, "The Advent of 3-D Package Age", Proc 26th IEEE/CPMT Int'l Electronic Manufacturing Technology Symposium, Santa Clara, 2000, pp. 102-107.
12. http://www.itrs.net/Links/2007ITRS/Home2007.htm