Thermo-mechanical behavior of through silicon vias in a 3D integrated package with inter-chip microbumps

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1190-1195

  Liu, Xi ^a   Chen, Qiao ^b   Sundaram, Venkatesh ^c   Simmons Matthews, Margaret ^d   Wachtler, Kurt P ^d   Tummala, Rao R ^b,c   Sitaraman, Suresh K ^a  

^a GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^b Georgia Institute of Technology   (United States)

^c GEORGIA INSTITUTE OF TECHNOLOGY   (United States)

^d TEXAS INSTRUMENTS   (United States)

Author keywords

3D Packaging; Finite Element Modeling; Thermo Mechanical Stress Analysis; Through Silicon Via

Indexed keywords

3-D SYSTEM INTEGRATION; 3D PACKAGING; ENABLING TECHNOLOGIES; FINITE ELEMENT MODELING; FINITE-ELEMENT MODELS; FREE-STANDING WAFERS; INTER-CHIP; MICRO-BUMPS; ORGANIC SUBSTRATE; SOLDER BUMP; STRESS/STRAIN; THERMO-MECHANICAL; THERMO-MECHANICAL ANALYSIS; THERMO-MECHANICAL BEHAVIORS; THERMO-MECHANICAL STRESS; THROUGH SILICON VIAS; THROUGH-SILICON-VIA;

CHIP SCALE PACKAGES; FINITE ELEMENT METHOD; INTEGRATION; INTERCONNECTION NETWORKS; PACKAGING; SILICON WAFERS; STRESS ANALYSIS;

THREE DIMENSIONAL;

EID: 79960403405     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898661     Document Type: Conference Paper

References (17)

1. Maakoto Motoyoshi, "Through-silicon via (TSV) ", Proceedings of the IEEE, Volume 97, pp. 43-48, 2009.
2. John H. Lau, "State-of-the-art and trends in throughsilicon via (TSV) and 3D integrations", ASME international mechanical engineering congress & exposition (IMECE), Vancouver, Canada, November, 2010
3. M Koyanagi, T Fukushima, T Tanaka, "High-density through silicon vias for 3-D LSIs", Proceedings of the IEEE, Volume 97, pp. 49-59, 2009.
4. P. R. Morrow, C.-M. Park, S. Ramanathan, M. J. Kobrinsky, and M. Harmes, "Three-Dimensional Wafer Stacking Via Cu-Cu Bonding Integrated With 65-nm Strained-Si/Low-k CMOS Technology", IEEE Electron Device Letters, VOL. 27, NO. 5, PP. 335-337, 2006
5. Dixit, P., Sun, Y., Miao, J., Pang, H. L, Chatterjee, R., and Rao R. Tummala, R. R, "Numerical and Experimental Investigation of Thermomechanical Deformation in High-Aspect-Ratio Electroplated Through-Silicon Vias", J. Electrochem. Soc., Volume 155, Issue 12, pp. H981-H986 (2008).
6. Tomasz, F., Kazimierz, F., Norman, M., Stephan, W., "TSV constraints related to temperature excursion, pressure during molding, materials used and handling loads", Microsystem Technologies, Volume 15, Number 1, January 2009, pp. 181-190 (10).
7. Wunderle, B., Mrossko, R., Wittler, O., Kaulfersch, E., Ramm, P., Michel, B., Reichl, H., "Thermo-Mechanical Reliability of 3D-integrated Microstructures in Stacked Silicon", Materials Research Society symposia proceedings, vol. 970, Paper 0970-Y02-04.
8. Ranganathan, N., Prasad, K., Balasubramanian, N., Pey, K. L, "A study of thermo-mechanical stress and its impact on through-silicon vias", Journal of Micromechanics and Microengineering, (13pp) 2008.
9. Selvanayagam, C. S., Lau, J. H., Zhang, X., Seah, S. K. W., Vaidyanathan, K., Chai, T. C., "Nonlinear thermal stress/strain analyses of copper filled TSV (through silicon via) and their flip-chip microbumps", Electronic Components and Technology Conference, 2008. ECTC 2008. 1073-1081.
10. Cheryl S. Selvanayagam, John H. Lau, Xiaowu Zhang, S. K. W. Seah, Kripesh Vaidyanathan, and T. C. Chai, "Nonlinear Thermal Stress/Strain Analyses of Copper Filled TSV (Through Silicon Via) and their Flip-Chip Microbumps", IEEE Transactions on Advanced Packaging, pp. 1073-1081, 2008
11. Xi Liu, Qiao Chen, Pradeep Dixit, Ritwik Chatterjee, Rao R. Tummala, and Suresh K. Sitaraman, "Failure Mechanisms and Optimum Design for Electroplated Copper Through-Silicon Vias (TSV) ", 59th Electronic Components and Technology Conference, San Diego, CA, May, 2009
12. Xi Liu, Qiao Chen, Venkatesh Sundaram, Sriram Muthukumar, Rao R. Tummala, and Suresh K. Sitaraman, "Reliable design of electroplated copper through silicon vias", ASME international mechanical engineering congress & exposition (IMECE), Vancouver, Canada, November, 2010
13. Xi Liu, Jiantao Zheng, Suresh K. Sitaraman, "Hygro-Thermo-Mechanical Reliability Assessment of a Thermal Interface Material for a Ball Grid Array Package Assembly", Journal of Electronic Packaging, Vol. 132, 2010
14. Kuan H. Lu, Suk-Kyu Ryu, Qiu Zhao, Xuefeng Zhang, Jay Im, Rui Huang, Paul S. Ho, "Thermal Stress Induced Delamination of Through Silicon Vias in 3-D Interconnects", 60th Electronic Components and Technology Conference, Las Vegas, May, 2010
15. Jin Yang, and I. Charles Ume, "Thermomechanical Reliability Study of Flip Chip Solder Bumps: Using Laser Ultrasound Technique and Finite Element Method", IEEE Transactions on Advanced Packaging, Vol. 32, No. 4, pp. 729-739, Nov. 2009.
16. th Electronic Components and Technology Conference (ECTC), 2010
17. Zhaozhi Li, Paul Houston, Daniel Baldwin, Gene Stout, Ted Tessier and John Evans, "Processing and Reliability Characterization of a 3D-WLCSP Packaged Component", Proceedings of the 59th Electronic Components and Technology Conference, San Diego, CA, May 26-29, 2009.