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Volumn , Issue , 2010, Pages 1273-1280
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TSV stress testing and modeling
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Author keywords
[No Author keywords available]
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Indexed keywords
3D INTERCONNECT;
CMOS CHIPS;
DIGITAL IMAGE;
EMERGING TECHNOLOGIES;
FINITE-ELEMENT METHOD MODELING;
MEASUREMENT SETUP;
OPTIMUM COMBINATION;
POWER CONSUMPTION;
PROCESSING EFFECTS;
SEMI-CONDUCTOR WAFER;
STRESS PROFILE;
STRESS SENSOR;
STRESS TESTING;
TEST ELEMENT GROUPS;
THROUGH SILICON VIAS;
COMPUTER CRIME;
DIGITAL IMAGE STORAGE;
FINITE ELEMENT METHOD;
INTEGRATION;
MILITARY PHOTOGRAPHY;
SILICON WAFERS;
THREE DIMENSIONAL;
TECHNOLOGY;
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EID: 77955225792
PISSN: 05695503
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/ECTC.2010.5490650 Document Type: Conference Paper |
Times cited : (14)
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References (5)
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