A 300-mm wafer-level three-dimensional integration scheme using tungsten through-silicon via and hybrid cu-adhesive bonding

Technical Digest - International Electron Devices Meeting, IEDM

Volumn , Issue , 2008, Pages

  Liu, F ^a   Yu, R R ^a   Young, A M ^a   Doyle, J P ^a   Wang, X ^b   Shi, L ^a   Chen, K N ^a   Li, X ^b   Dipaola, D A ^b   Brown, D ^b   Ryan, C T ^b   Hagan, J A ^b   Wong, K H ^b   Lu, M ^a   Gu, X ^a   Klymko, N R ^b   Perfecto, E D ^b   Merryman, A G ^b   Kelly, K A ^b   Purushothaman, S ^a   Koester, S J ^a   Wisnieff, R ^a   Haensch, W ^a   more..

^a IBM T J WATSON RESEARCH CENTER   (United States)

^b IBM RESEARCH   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3D SYSTEMS; ADHESIVE BONDINGS; CRITICAL DIMENSIONS; FINE PITCHES; HIGH ASPECT RATIOS; HIGH-SPEED SIGNALING; POWER DELIVERIES; THREE-DIMENSIONAL INTEGRATIONS; THROUGH-SILICON VIAS; WAFER LEVELS;

ASPECT RATIO; ELECTRIC POWER TRANSMISSION; ELECTRON DEVICES; ELECTRONICS PACKAGING; PHOTORESISTS; SEMICONDUCTING SILICON COMPOUNDS; SILICON WAFERS; THREE DIMENSIONAL; TUNGSTEN;

WAFER BONDING;

EID: 64549139638     PISSN: 01631918     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IEDM.2008.4796762     Document Type: Conference Paper

References (5)

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