Effects of TSV interposer on the reliability of 3D IC integration SiP

ASME 2011 Pacific Rim Technical Conference and Exhibition on Packaging and Integration of Electronic and Photonic Systems, InterPACK 2011

Volumn 1, Issue , 2011, Pages 65-73

  Lau, John H ^a   Zhang, Xiaowu ^b  

^a INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE   (Taiwan)

^b INSTITUTE OF MICROELECTRONICS   (Singapore)

Author keywords

[No Author keywords available]

Indexed keywords

CREEP STRAIN; MOORE'S LAW; SOLDER JOINTS; SYSTEM-IN-PACKAGE; TEST VEHICLE; THERMAL CYCLING TEST; THROUGH SILICON VIAS;

EXHIBITIONS; INTEGRATION; INTERNET PROTOCOLS; THREE DIMENSIONAL;

CHIP SCALE PACKAGES;

EID: 84860326032     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1115/IPACK2011-52205     Document Type: Conference Paper

References (73)

1. Lau, J. H., Reliability of RoHS Compliant 2D & 3D IC Interconnects, McGraw-Hill, NY, 2011.
2. Lau, J. H., C. K. Lee, C. S. Premachandran, A. Yu, Advanced MEMS Packaging, McGraw-Hill, NY, 2010.
3. Lau, J. H., "Critical Issues of TSV and 3D IC Integration", IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 35-43.
4. Lau, J. H., "Design and Process of 3D MEMS System-in-Package (SiP)", IMAPS Transactions, Journal of Microelectronics and Electronic Packaging, First Quarter Issue, 2010, pp. 10-15.
5. Lau, J. H., Lee, R., Yuen, M., and Chan, P., "3D LED and IC Wafer Level Packaging", Journal of Microelectronics International, Vol. 27, Issue 2, 2010, pp. 98-105.
6. Lau, J. H., "State-of-the-art and Trends in 3D Integration", Chip Scale Review, March/April, 2010, pp. 22-28.
7. Lau, J. H., Y. S. Chan, and R. S. W. Lee, "3D IC Integration with TSV Interposers for High-Performance Applications", Chip Scale Review, September/October, 2010, pp. 26-29.
8. Lau, J. H., Lim, Y., Lim, T., Tang, G., Khong, C., Zhang, X., Ramana, P., Zhang, J., Tani, C., Chandrappan, J., Chai, J., Li, J., Tangdiongga, G., and Kwong, D. "Design and analysis of 3-D stacked optoelectronics on optical printed circuit boards." In Proceedings of SPIE, Photonics Packaging, Integration, and Interconnects VIII, San Jose, CA, January 19-24, 2008, Vol. 6899, pp. 07.1-07.20
9. and accepted for IEEE Transactions in Advanced Packaging.
10. Lau, J. H., "Overview of TSV and 3D IC Integration", Journal of Microelectronics International, (in press).
11. Lau, J. H., M. S. Zhang, and S. W. R. Lee, "Embedded 3D Hybrid IC Integration System-in-Package (SiP) for OptoElectronic Interconnects in Organic Substrates", ASME Paper no. IMECE2010-40974,
12. and accepted for ASME Transactions, Journal of Electronic Packaging.
13. Lau, J. H., Yue, T. G., Hoe, G. Y. Y., Zhang, X. W., Chong, C. T., Damaruganath, P., and Vaidyanathan, K. "Effects of TSV (Through Silicon Via) Interposer/Chip on the Thermal Performances of 3-D IC Packaging." ASME Paper no. IPACK2009-89380.
14. Lau, J. H., "State-of-the-art and Trends in Through-Silicon Via (TSV) and 3D Integrations, ASME Paper no. IMECE2010-37783.
15. Lau, J. H., Y. S. Chan, and S. R. Lee, "Thermal-Enhanced and Cost-Effective 3D IC Integration with TSV (Through-Silicon Via) Interposers for High-Performance Applications", ASME Paper no. IMECE2010-40975.
16. Lau, J. H., "Key Enabling Technologies for 3D IC Integrations", PDC at IEEE/ECTC, May 2009.
17. Lau, J. H., "3D IC Integration and WLP", PDC at IEEE/ECTC, May 2010.
18. Lau, J. H., "Critical Issues of 3D IC Integrations", International Symposium on Microelectronics, San Jose, CA, November 2009, pp. 585-592.
19. Lau, J. H., "Design and Process of 3D MEMS Packaging", International Symposium on Microelectronics, San Jose, CA, November 2009, pp. 1-9.
20. Lau, J. H., and Tang, G., "Thermal Management of 3D IC Integration with TSV (Through Silicon Via)", IEEE Proceedings of ECTC, San Diego, May 2009, pp. 635-640.
21. Lau, J. H., "TSV Manufacturing Yield and Hidden Costs for 3D IC Integration", IEEE Proceedings of ECTC, Las Vegas, NV, June 2010, pp. 1031-1041.
22. Lau, J. H., X. Zheng, and C. Selvanayagam, "Failure Analyses of 3D SiP (System-in-Package) and WLP (Wafer-Level Package) by Finite Element Methods", IEEE International Physics and Failure Analyses, 2009, pp. 1-8 (invited paper).
23. Lau, J. H., "Evolution and Outlook of 3D Si/IC Integration", IEEE Electronic Packaging and Technology Conference, 2010, pp. 560-570, (invited paper).
24. Lau, J. H., "3D Si/IC Integration", IEEE/EDAPS, December 8, 2010, (keynote).
25. Yu, A., J. H. Lau, Ho, S., Kumar, A., Wai, Y., Yu, D., Jong, M., Kripesh, V., Pinjala, D., Kwong, D., "Study of 15-μm-pitch solder microbumps for 3D IC integration." IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 6-10.
26. Yu, A., J. H. Lau, Ho, S., Kumar, A., Yin, H., Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., "Three dimensional interconnects with high aspect ratio TSVs and fine pitch solder microbumps." IEEE Proceedings of ECTC, San Diego, CA, May 2009, pp. 350-354.
27. Also, accepted for publication in IEEE Transactions in Advanced Packaging.
28. Yu, A., A. Kumar, S. Ho, H. Yin, J. H. Lau, Ching, J., Kripesh, V., Pinjala, D., Chen, S., Chan, C., Chao, C., Chiu, C., Huang, M., and Chen, C., "Development of Fine Pitch Solder Microbumps for 3D Chip Stacking", IEEE EPTC Proceedings, Singapore, December 2008, pp. 387-392.
29. Also, accepted for publication in IEEE Transactions in Advanced Packaging.
30. Yu, A., N. Khan, G. Archit, D. Pinjalal, K. Toh, V. Kripesh, S. Yoon, and J. H. Lau, "Development of silicon carriers with embedded thermal solutions for high power 3-D package." IEEE Transactions on Components and Packaging Technology, Vol. 32, No. 3, September 2009, pp. 566-571.
31. Tang, G., O. Navas, D. Pinjala, J. H. Lau, A. Yu, and V. Kripesh, "Integrated Liquid Cooling Systems for 3-D Stacked TSV Modules", IEEE Transactions on Components and Packaging Technologies, Vol. 33, Issue 1, 2010, pp. 184-195.
32. Chen, K., C. Premachandran, K. Choi, C. Ong, X. Ling, A. Khairyanto, B. Ratmin, P. Myo, and J. H. Lau, "C2W Bonding Method for MEMS Applications", IEEE Proceedings of ECTC, December 2008, pp. 1283-1287.
33. Premachandran, C. S., J. H. Lau, X. Ling, A. Khairyanto, K. Chen, and Myo Ei Pa Pa, "A Novel, Wafer-Level Stacking Method for Low-Chip Yield and Non-Uniform, Chip-Size Wafers for MEMS and 3D SIP Applications", IEEE Proceedings of ECTC, Orlando, FL, May 27-30, 2008, pp. 314-318.
34. Zhang, X., T. Chai, J. H. Lau, C. Selvanayagam, K. Biswas, S. Liu, D. Pinjala, G. Tang, Y. Ong, S. Vempati, E. Wai, H. Li, B. Liao, N. Ranganathan, V. Kripesh, J. Sun, J. Doricko, and C. Vath, "Development of Through Silicon Via (TSV) Interposer Technology for Large Die (21×21mm) Fine-pitch Cu/low-k FCBGA Package", IEEE Proceedings of ECTC, May, 2009, pp. 305-312.
35. Also, IEEE Transactions in Advanced Packaging (in press.)
36. Hoe, G., G. Tang, P. Damaruganath, C. Chong, J. H. Lau, X. Zhang, and K. Vaidyanathan, "Effect of TSV Interposer on the Thermal Performance of FCBGA Package", IEEE Proceedings of Electronics Packaging and Technology Conference, Singapore, December 2009, pp. 778-786.
37. Kumar, A., X. Zhang, Q. Zhang, M. Jong, G. Huang, V. Kripesh, C. Lee, J. H. Lau, D. Kwong, V. Sundaram, R. Tummula, and M. Georg (2008), "Evaluation of Stresses in Thin Device Wafer using Piezoresistive Stress Sensor," IEEE Proceedings of EPTC, December, pp. 1270-1276,
38. and IEEE Transactions in Components and Packaging Technologies, (in press.)
39. Vempati1, S. R., S. Nandar, C. Khong, Y. Lim, K. Vaidyanathan, J. H. Lau, B. P. Liew, K. Y. Au, S. Tanary, A. Fenne, R. Erich, and J. Milla, "Development of 3-D Silicon Die Stacked Package Using Flip Chip Technology with Micro Bump Interconnects", IEEE Proceedings of ECTC San Diego, CA, May, 2009, pp. 980-987.
40. Also, accepted for publication in IEEE Transactions in CPMT.
41. Khan, N., L. Yu, P. Tan, S. Ho, N. Su, H. Wai, K. Vaidyanathan, D. Pinjala, J. H. Lau, T. Chuan, "3D Packaging with Through Silicon Via (TSV) for Electrical and Fluidic Interconnections", IEEE Proceedings of ECTC, San Diego, CA, May, 2009, pp. 1153-1158.
42. Sekhar, V. N., S. Lu, A. Kumar, T. C. Chai, V. Lee, S. Wang, X. Zhang, C. S. Premchandran, V. Kripesh, and J. H. Lau, "Effect of Wafer Back Grinding on the Mechanical Behavior of Multilayered Low-k for 3D-Stack Packaging Applications", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1517-1524.
43. Khan, N., V. Rao, S. Lim, S. Ho, V. Lee, X. Zhang, R. Yang, E. Liao, Ranganathan, T. Chai, V. Kripesh, and J. H. Lau, "Development of 3D Silicon Module with TSV for System in Packaging", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 550-555.
44. Ho, S., S. Yoon, Q. Zhou, K. Pasad, V. Kripesh and J. H. Lau, "High RF Performance TSV for Silicon Carrier for High Frequency Application", IEEE Proceedings of Electronic, Components & Technology Conference, Orlando, FL, May 27-30, 2008, pp. 1956-1952.
45. Lim, S., V. Rao, H. Yin, W. Ching, V. Kripesh, C. Lee, J. H. Lau, J. Milla and A. Fenner, "Process Development and Reliability of Microbumps," IEEE Transactions in Components and Packaging Technology, Vol. 33, No. 4, December 2010, pp. 747-753.
46. Selvanayagam, C., J. H. Lau, X. Zhang, S. Seah, K. Vaidyanathan, and T. Chai, "Nonlinear Thermal Stress/Strain Analysis of Copper Filled TSV (Through Silicon Via) and Their Flip-Chip Microbumps", IEEE Transactions in Advanced Packaging, Vol. 32, No. 4, November 2009, pp. 720-728.
47. Made, R., Gan, C. L., Yan, L., Yu, A., Yoon, S. U., Lau, J. H., and Lee, C. "Study of low temperature thermocompression bonding in Ag-In solder for packaging applications." Journal of Electronic Materials, 38:365-371, 2009.
48. Yan, L.-L., Lee, C.-K., Yu, D.-Q., Yu, A.-B., Choi, W.-K., Lau, J. H., and Yoon, S.-U. "A hermetic seal using composite thin solder In/Sn as intermediate layer and its interdiffusion reaction with Cu." Journal of Electronic Materials. 38:200-207, 2009.
49. Yan, L.-L., Lee, V., Yu, D., Choi, W. K., Yu, A., Yoon, S.-U., and Lau, J. H. "A hermetic chip to chip bonding at low temperature with Cu/In/Sn/Cu joint." In IEEE Proceedings of Electronics and Components Technology Conference, Orlando, FL, May 2008, pp. 1844-1848.
50. Yu, A., Lee, C., Yan, L., Made, R., Gan, C., Zhang, Q., Yoon, S., and Lau, J. H. "Development of wafer level packaged scanning micromirrors." Proc. Photon. West 6887:1-9, 2008.
51. Lee, C., Yu, A., Yan, L., Wang, H., Han, J., Zhang, Q., and Lau, J. H. "Characterization of intermediate In/Ag layers of low temperature fluxless solder based wafer bonding for MEMS packaging." J. Sensors Actuators (in press).
52. Yu, D.-Q., Lee, C., Yan, L. L., Choi, W. K., Yu, A., and Lau, J. H. "The role of Ni buffer layer on high yield low temperature hermetic wafer bonding using In/Sn/Cu metallization." Appl. Phys. Lett., Vol. 94, Issue 3, Jan 2009, pp. 34105-34105-3.
53. Yu, D. Q., Yan, L. L., Lee, C., Choi, W. K., Yoon, S. U., and Lau, J. H. "Study on high yield wafer to wafer bonding using In/Sn and Cu metallization." In Proceedings of the Eurosensors Conference, Dresden, Germany, 2008, pp. 1242-1245.
54. Yu, D., Yan, L., Lee, C., Choi, W., Thew, M., Foo, C., and Lau, J. H. "Wafer level hermetic bonding using Sn/In and Cu/Ti/Au metallization." In IEEE Proceeding of Electronics Packaging and Technology Conference, Singapore, December 2008, pp. 1-6.
55. Choi, W., Yu, D., Lee, C., Yan, L., Yu, A., Yoon, S., Lau, J. H., Cho, M., Jo, Y., and Lee, H. "Development of low temperature bonding using In-based solders." In IEEE Proceedings of Electronics Component and Technology Conference, Orlando, FL, May 2008, pp. 1294-1299.
56. Choi, W., Premachandran, C., Ong, C., Ling, X., Liao, E., Khairyanto, A., Chen, K., Thaw, P., and Lau, J. H. "Development of novel intermetallic joints using thin film indium based solder by low temperature bonding technology for 3D IC stacking." In IEEE Proceedings of Electronics Component and Technology Conference, San Diego, CA, May 2009, pp. 333-338.
57. Zhang, X., A. Kumar, Q. X. Zhang, Y. Y. Ong, S. W. Ho, C. H. Khong, V. Kripesh, J. H. Lau, D.-L. Kwong, V. Sundaram, Rao R. Tummula, Georg Meyer-Berg, "Application of Piezoresistive Stress Sensors in Ultra Thin Device Handling and Characterization," Journal of Sensors & Actuators: A. Physical, Vol. 156, Nov. 2009, pp. 2-7.
58. Lau, J. H., H. Chieh, and R. Tain, "TSV Interposers with Embedded Microchannels for 3D IC and Multiple High-Power LEDs Integration SiP", ASME Paper no. InterPACK2011-52204, (to be published).
59. Lau, J. H., "The Most Cost-Effective Integrator (TSV Interposer) for 3D IC Integration SiP", ASME Paper no. InterPACK2011-52189, (to be published).
60. Zhang, X., R. Rajoo, C. Selvanayagam, A. Kumar, V. Rao, N. Khan, V. Kripesh, J. H. Lau, D.-L. Kwong, V. Sundaram, R. Tummula, "Application of Piezoresistive Stress Sensor in Wafer Bumping and Drop Impact Test of Embedded Ultra Thin Device", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
61. Chieh, H., Y. Chao, J. H. Lau, R. Tain, M. Dai, R. Lo, and M. Kao, "Equivalent Thermal Conductivities and Design Guidelines for Through Silicon Vias (TSVs) in 3D IC Integration", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
62. Hsin, E., J. Chen, J. H. Lau, S. Shen, Y. Hsu, S. Chen, C. Wn, J. Chen, K. Lin, T. Ku, and M. Kao, "Effects of Etch Rate on Scallop of Through-Silicon Vias (TSVs) in a 300mm Wafer", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
63. Chen, J. Chen, P. Tzeng, S. Chen, C. Wu, C. Chen, C. Lin, J. H. Lau, Y. Hsin, T. Ku, and M. Kao, "Impact of Slurry in Cu CMP (Chemical Mechanical Polishing) on Cu Topography of Through Silicon Vias (TSVs) and Redistributed Layers", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
64. Tsai, W., H. Chang, C. Chien, J. H. Lau, H. Fu, C. Chiang, T. Kuo, Y. Chen, R. Lo, and M. Kao, "How to Select Adhesive Materials for Temporary Bonding and De-Bonding of Thin-Wafer Handling in 3D IC Integration?", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
65. Lee, C, T. Chang, S. Lu, Z. Hsiao, J. Huang, C. Zhan, J. H. Lau, C. Ko, T. Chen, Y. Chen, R. Lo, and M. Kao, "Characterization and Reliability Assessment of Fine-Pitch Lead-Free Solder Microbumps for 3D IC Integration", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
66. Huang, S., T. Chang, R. Cheng, J. Chang, C. Fan, C. Zhan, J. H. Lau, T. Chen, W. Lo, and M. Kao, "Failure Mechanism of 20μm Pitch Microjoint within a Chip Stacking Architecture", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
67. Lin, Y., C. Zhan, J. Juang, J. H. Lau, T. Chen, R. Lo, M. Kao, T. Tian, and K. Tu, "Electromigration in Ni/Sn intermetallic micro bump joint for 3D IC chip stacking", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
68. Zhan, C, J. Juang, Y. Lin, Y. Huang, K. Kao, T. Yang, S. Lu, J. H. Lau, T. Chen, R. Lo, and M. J. Kao, "Development of fluxless chip-on-wafer bonding process for 3DIC chip stacking with 30μm pitch lead-free solder micro bumps and reliability characterization", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference.
69. Lau, J. H., "TSV and other Key Enabling Technologies for 3D Si/IC Integration", to be presented and published in IEEE Proceedings of Electronics Component and Technology Conference, 4-hour Professional Development Course.
70. Lau, J. H., M. Dai, Y. Chao, W. Li, S. Wu, J. Hung, M. Hsieh, J. Chien, R. Tain, C. Tzeng, K. Lin, E. Hsin, C. Chen, M. Chen, C. Wu, J. Chen, J. Chien, C. Chiang, Z. Lin, L. Wu, H. Chang, W. Tsai, C. Lee, T. Chang, C. Ko, T. Chen, S. Sheu, S. Wu, Y. Chen, R. Lo, T. Ku, M. Kao, F. Hsieh, and D. Hu, "Feasibility Study of a 3D IC Integration System-in-Packaging (SiP)", to be presented and published in IEEE/ICEP Proceedings, Nara, Japan, April 13, 2011.
71. Lau, J. H., "Evolution and Outlook of 3D IC/Si Integration", to be presented at CSTIC (Keynote), Shanghai, China.
72. Lau, J. H., "Evolution, Outlook, and Challenges of 3D IC/Si Integration", to be published and presented at IEEE/ICEP (Keynote), Nara, Japan, April 13, 2011.
73. Dorsey, P., "Xilinx Stacked Silicon Interconnect Technology Delivers Breakthrough FPGA Capacity, Bandwidth, and Power Efficiency", Xilinx White Paper: Virtex-7 FPGAs, WP380 (v1) October 27, 2010, pp. 1-10.