Yield modeling of 3D integrated wafer scale assemblies

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2010, Pages 1935-1938

  Campbell, David V ^a  

^a SANDIA NATIONAL LABORATORIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; ASSEMBLY PROCESS; DIE ASSEMBLY; DIE SIZE; DIE STACK; MODEL RESULTS; MONTE CARLO MODEL; NUMBER OF LAYERS; WAFER SCALE; YIELD MODELING;

DIES; MONTE CARLO METHODS;

THREE DIMENSIONAL;

EID: 77955210741     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2010.5490688     Document Type: Conference Paper

References (4)

1. Metropolis, N.; Ulam, S. (1949). "The Monte Carlo Method". Journal of the American Statistical Association, Vol.44, pg 335-341.
2. Web published Technology and Defect Trends, IC Knowledge.
3. Gregory Smith, Larry Smith, "Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration", IEEE Trans on Very Large Scale Integration Systems, Vol 17, No.9, pg 1357-1362, September 2009.
4. P. Mercier, S.R. Singh, K. Iniewski, B. Moore, P. O'Shea, "Yield and Cost Modeling for 3D Chip Stack Technologies", IEEE 2006 Custom Integrated Circuits Conference, pg 357-360.