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Volumn , Issue , 2009, Pages 778-786

Effect of TSV interposer on the thermal performance of FCBGA package

Author keywords

[No Author keywords available]

Indexed keywords

COMPACT MODELING; CONDUCTIVE FILLERS; DETAILED MODELING; EQUIVALENT THERMAL; FCBGA PACKAGES; FINE PITCH; MODELING APPROACH; PLATING THICKNESS; THERMAL PERFORMANCE; THERMAL RESISTANCE; THROUGH-SILICON-VIA;

EID: 77950959311     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/EPTC.2009.5416445     Document Type: Conference Paper
Times cited : (43)

References (7)
  • 2
    • 77950921463 scopus 로고    scopus 로고
    • International Technology Roadmap for Semiconductors (ITRS), http://www.itrs.net
  • 3
    • 61749088463 scopus 로고    scopus 로고
    • Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication
    • Ranganathan, N., et, al. 'Integration of High Aspect Ratio Tapered Silicon Via for Silicon Carrier Fabrication.' IEEE Transactions on Advanced Packaging, Vol.32, No.1, 2009, p62-71.
    • (2009) IEEE Transactions on Advanced Packaging , vol.32 , Issue.1 , pp. 62-71
    • Ranganathan, N.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.