System on wafer: A new silicon concept in SiP

Proceedings of the IEEE

Volumn 97, Issue 1, 2009, Pages 60-69

  Poupon, Gilles ^a   Sillon, Nicolas ^a   Henry, David ^a   Gillot, Charlotte ^a   Mathewson, Alan ^a   Di Cioccio, Lea ^a   Charlet, Barbara ^a   Leduc, Patrick ^a   Vinet, Maud ^a   Batude, Perrine ^a  

^a CEA LETI   (France)

Author keywords

3 D integration; Micro insert; System in package; System on wafer; Thin film packaging; Through silicon vias

Indexed keywords

CHIP SCALE PACKAGES; COOLING SYSTEMS; ELECTROMECHANICAL DEVICES; FLIP CHIP DEVICES; MEMS; SILICON WAFERS; SUBSTRATES; THREE DIMENSIONAL INTEGRATED CIRCUITS;

3-D INTEGRATION; MICRO INSERT; ON-WAFER; THIN FILM PACKAGING; THROUGH SILICON VIAS;

SYSTEM-IN-PACKAGE;

EID: 61549125296     PISSN: 00189219     EISSN: None     Source Type: Journal    
DOI: 10.1109/JPROC.2008.2007464     Document Type: Article

References (17)

1. R. Tummala and Al, "High density packaging in 2010 and beyond," in Proc. IEEE 2002 Int. Symp. Electron. Mater. Packag, pp. 30-36.
2. N. Sillon and Al, "Innovative flip chip solution for system on wafer concept," in Proc. 3S Workshop, Atlanta, GA, 2005.
3. J. C. Souriau and Al, "Wafer level processing of 3D system in package for RF and data applications," in Proc. ECTC, Orlando, FL, 2005.
4. K. Najafi, "Micropackaging technologies for integrated microsystems: Applications to MEMS and MOEMS," in Proc. SPIE Micromach. Microfab. Process Technol. VII, 2003.
5. Gillot, N. Sillon, P. Robert, E. Dahan, X. Baillin, and E. Lagoutte, "Wafer level hermetic packaging for above-IC RF MEMS: Process and characterization," in Proc. IMAPS Int. Workshop Microelectron., Long Beach, CA, Nov. 14-18, 2004.
6. E. Laine, K. Ruhmer, E. Perfecto, H. Longworth, and D. Hawken, "C4NP as a high-volume manufacturing method for fine-pitch and lead-free flipchip solder bumping," in Proc. Electron. System Integr. Technol. Conf., Dresden, Germany, 2006, pp. 518-524.
7. A. Mathewson, J. Brun, C. Puget, R. Franiatte, N. Sillon, F. Deputot, and B. Dubois-Bonvalot, "Microstructured interconnections for high security systems," in Proc. IEEE Electron. Syst. Integr. Conf. (ESTC), Dresden, Germany, 2006.
8. P. A. Gruber, L. Beélanger, G. P. Brouillette, D. H. Danovitch, J.-L. Landreville, D. T. Naugle, V. A. Oberson, D.-Y. Shih, C L. Tessler, and M. R. Turgeon, "Low-cost wafer bumping," IBM J. Res. Dev., vol. 49, no. 4/5, pp. 622-639, Jul./Sep. 2005.
9. R. R. Tummala, P. M. Raj, A. Aggarwal, G. Mehrotra, S. W. Koh, S. Bansal, T. T. Tiong, C. K. Ong, J. Chew, K. Vaidyanathan, and V. S. Rao, "Copper interconnections for high performance and fine pitch flip-chip digital applications and ultra-miniaturized RF module applications, " in Proc. IEEE ECTC, 2006, pp. 102-111.
10. M. Vinet, T. Poiroux et al., "Bonded planar double metal gate NMOS transistors down to 10 nm," IEEE Electron Device Lett., vol. 26, pp. 317-319, 2005.
11. B. Charlet, L. Di Cioccio et al., "Chip-to-chip interconnections based on the wireless capacitive coupling for 3D integration," in Proc. MAM, Grenoble, France, 2006.
12. R. Chatterjee, M. Fayolle et al., "Three dimensional chip stacking using a wafer-to-wafer integration," in Proc. IITC 2007.
13. P. Leduc, F. de Crécy et al., "Challenges for 3D IC integration: Bonding quality and thermal management," in Proc. IITC 2007.
14. Photonic interconnect layer on CMOS by wafer-scale integration (PICMOS). [Online]. Available: http://picmos.intec.ugent.be
15. L. Di Cioccio, "New heterostructures and 3D devices obtained by the bonding and thinning technique," Proc. 220th ECS Wafer Bonding Conf. 2006.
16. L. Clavelier, J. P. Joly, and O. Faynot, "Circuit intégré tridimensionnel de type CMOS et procédé de fabrication, FRA0600577.
17. F. Grossi, L. di Cioccio et al., "Self assembly of die to wafer using direct bonding methods and capillarity techniques," in Proc. IMAPS 2006.