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Volumn , Issue , 2010, Pages
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Wafer and/or chip bonding adhesives for 3D package
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Author keywords
[No Author keywords available]
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Indexed keywords
3-D PACKAGES;
ALIGNMENT MARKS;
BONDING PROCESS;
CHIP BONDING;
CONDUCTIVE SHEET;
FLOWABILITY;
HIGH HEAT RESISTANCE;
LOW COEFFICIENT OF THERMAL EXPANSIONS;
THERMAL CYCLE;
WAFER LEVEL PROCESS;
WAFER SURFACE;
WEIGHT LOSS TEMPERATURES;
ALIGNMENT;
HEAT RESISTANCE;
LAMINATING;
PHOTOLITHOGRAPHY;
THERMAL EXPANSION;
THREE DIMENSIONAL;
WAFER BONDING;
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EID: 79251564471
PISSN: None
EISSN: None
Source Type: Conference Proceeding
DOI: 10.1109/CPMTSYMPJ.2010.5679534 Document Type: Conference Paper |
Times cited : (11)
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References (2)
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