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Volumn , Issue , 2010, Pages

Wafer and/or chip bonding adhesives for 3D package

Author keywords

[No Author keywords available]

Indexed keywords

3-D PACKAGES; ALIGNMENT MARKS; BONDING PROCESS; CHIP BONDING; CONDUCTIVE SHEET; FLOWABILITY; HIGH HEAT RESISTANCE; LOW COEFFICIENT OF THERMAL EXPANSIONS; THERMAL CYCLE; WAFER LEVEL PROCESS; WAFER SURFACE; WEIGHT LOSS TEMPERATURES;

EID: 79251564471     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/CPMTSYMPJ.2010.5679534     Document Type: Conference Paper
Times cited : (11)

References (2)


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.