Chip-to-wafer (C2W) 3D integration with well-controlled template alignment and wafer-level bonding

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2011, Pages 1-6

  Chen, Qianwen ^a,b   Zhang, Dingyou ^b   Wang, Zheyao ^a   Liu, Litian ^a   Lu, James Jian Qiang ^b  

^a TSINGHUA UNIVERSITY   (China)

^b RENSSELAER POLYTECHNIC INSTITUTE   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

3-D INTEGRATION; 3D SYSTEMS; ALIGNMENT ACCURACY; BENZOCYCLOBUTENE; BONDING INTERFACES; BONDING STRUCTURE; EDGE DEFINITION; HIGH THROUGHPUT; IV CHARACTERISTICS; KEY PROCESS; OHMIC BEHAVIOR; SPECIFIC CONTACT RESISTANCES; TEMPLATE FABRICATION; THERMAL CYCLE; THREE DIMENSIONAL (3D) INTEGRATION; WAFER LEVEL;

ALIGNMENT; BUTENES; ELECTRIC CONNECTORS; ELECTRIC SWITCHGEAR; INTEGRATION; TECHNOLOGY; THREE DIMENSIONAL;

WAFER BONDING;

EID: 79960396333     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898482     Document Type: Conference Paper

References (14)

1. J.-Q. Lu, "3-D Hyperintegration and Packaging Technologies for Micro-nano Systems", Proceedings of the IEEE, Vol. 97, No. 1 (2009), pp. 18-30.
2. A. W. Topol, D. C. La Tulipe, et al., "Three-dimensional Integrated Circuits", IBM J. Res. & Dev., Vol. 50, No. 4/5 (2006), pp. 491-506.
3. th Electronic Components and Technology Conf., Orlando, FL, May. 2001, pp. 541-546.
4. K. Sakuma, P. S. Andry, et al., "3D Chip-stacking Technology With Through-silicon Vias and Low-volume Lead-free interconnect", IBM J. Res. & Dev., Vol. 52, No. 6 (2008), pp. 611-622.
5. A. Klumpp, R. Merkel, et al., "Vertical System Integration by Using Inter-Chip Vias and Solid-Liquid Interdiffusion Bonding", Jpn. J. Appl. Phys., Vol. 43, No. 7A (2004), pp. 829-830.
6. th Electronic Components and Technology Conf., Las Vegas, NV, June. 2010, pp. 829-833.
7. th Asia and South Pacific Design Automation Conf., Yokohama, Japan, January. 2009, pp. 409-415.
8. S. J. Koester, A. M. Young, et al., "Wafer-level 3D Integration Technology", IBM J. Res. & Dev., Vol. 52, No. 6 (2008), pp. 583-597.
9. M. E. Mills, P. Townsend, et al., "Benzocyclobutene (DVS-BCB) Polymer as an Interlayer Dielectric (ILD) Material", Microelectronic Engineering, Vol. 33, No. 1-4 (1997), pp. 327-334.
10. A. Modafe, N. Ghalichechian, et al., "Embedded Benzocyclobutene in Silicon: An Integrated Fabrication Process for Electrical and Thermal Isolation in MEMS", Microelectronic Engineering, Vol. 82, No. 2 (2005), pp. 154-167.
11. 2 Plasma", J. Vac. Sci. Technol. B, Vol. 29, No. 1 (2011), pp. 011019.
12. M. Fayolle, F. Romagna, "Copper CMP Evaluation: Planarization Issues", Microelectronic Engineering, Vol. 37-38, (1997), pp. 135-141.
13. H. M. Ho, W. Lam, et al., "Direct gold and copper wires bonding on copper", Microelectronics Reliability, Vol. 43, No. 6 (2003), pp. 913-923.
14. K. N. Chen, C. S. Tan, et al., "Morphology and Bond Strength of Copper Wafer Bonding", Electrochemical and Solid-State Letters, Vol. 7, No. 1 (2004), pp. G14-G16.