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Volumn , Issue , 2011, Pages 573-576

Ceramics vs. low-CTE organic packaging of TSV silicon interposers

Author keywords

[No Author keywords available]

Indexed keywords

BOARD-LEVEL RELIABILITY; CORE MATERIAL; DIE STRESS; LOWER COST; LTCC (LOW TEMPERATURE CO-FIRED CERAMIC); LTCC-CERAMICS; MARKET ACCEPTANCE; MICRO-BUMPS; ORGANIC MATERIALS; ORGANIC PACKAGING; PACKAGE SIZE; SECOND LEVEL; SIMULATION RESULT; THROUGH-SILICON-VIA; WIRING DENSITY;

EID: 79960387923     PISSN: 05695503     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ECTC.2011.5898569     Document Type: Conference Paper
Times cited : (36)

References (14)
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  • 2
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    • Design guidance for the mechanical reliability of Low-k flip-chip BGA package
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    • Advanced reliability modeling of Cu/Low-k interconnection in FCBGA package
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    • Investigation of residual stress in wafer level interconnect structures induced by wafer processing
    • Wang G, Gan D, Groothuis S, Ho P S, "Investigation of residual stress in wafer level interconnect structures induced by wafer processing", IEEE, 2006.
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.