Networks on Chips

Networks on Chips

Volumn , Issue , 2006, Pages

  Benini, Luca ^a   De Micheli, Giovanni ^b   Bertozzi, Davide ^c   Cidon, Israel ^d   Goossens, Kees ^e   Kim, Kwanho ^f   Lee, Kangmin ^f   Lee, Se Joong ^f   Murali, Srinivasan ^g   Yoo, Hoi Jun ^f  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b EPFL   (Switzerland)

^c UNIVERSITY OF FERRARA   (Italy)

^d TECHNION ISRAEL INSTITUTE OF TECHNOLOGY   (Israel)

^e PHILIPS RESEARCH LABORATORIES   (Netherlands)

^f Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^g STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85013722801     PISSN: None     EISSN: None     Source Type: Book    
DOI: 10.1016/B978-0-12-370521-1.X5000-0     Document Type: Book

References (482)

1. Adriahantenaina A., Charlery H., Greiner A., Mortiezand L., Zeferino C. SPIN: A Scalable, Packet Switched, On-Chip Micro-network. DATE -Design, Automation and Test in Europe Conference and Exhibition 2003, 70-73.
2. Ajami A.H., Banerjee K., Pedram M. Modeling and Analysis of Nonuniform Substrate Temperature Effects on Global ULSI Interconnects. IEEE Transactions on CAD June 2005, Vol. 24(No. 6):849-861.
3. Bakoglu H. Circuits, Interconnections, and Packaging for VLSI 1990, Addison-Wesley.
4. Benini L., Bogliolo A., De Micheli G. A Survey of Design Techniques for System-Level Dynamic Power Management. IEEE Transactions on Very Large-Scale Integration Systems June 2000, Vol. 8(No. 3):299-316.
5. Cesario W.O., Lyonnard D., Nicolescu G., Paviot Y., Yoo S., Gauthier L., Diaz-Nava M., Jerraya A.A. Multiprocessor SoC Platforms: A Component-Based Design Approach. IEEE Design and Test of Computers November-December 2002, Vol. 19(No. 6):52-63.
6. Dally W., Towles B. Principles and Practices of Interconnection Networks 2004, Morgan Kaufmann, Upper Saddle River, NJ.
7. Dally W., Towles B. Route Packets, Not Wires: On-Chip Interconnection Networks. Proceedings of the 38th Design Automation Conference 2001.
8. Dally W.J., Aoki H. Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels. IEEE Transactions on Parallel and Distributed Systems April 1993, Vol. 4(No. 4):466-475.
9. Dally W., Seitz C. The Torus Routing Chip. Distributed Processing 1996, Vol. 1:187-196.
10. Dall'Osso M., Biccari G., Giovannini L., Bertozzi D., Benini L. Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multiprocessor SoCs. International Conference on Computer Design 2003, 536-539.
11. Ernst D., Das S., Lee S., Blaauw D., Austin T., Mudge T., Kim N.S., Flautner K. Razor: Circuit-Level Correction of Timing Errors for Low-Power Operation. IEEE Micro November-December 2004, Vol. 24(No. 6):10-20.
12. Dally W., Poulton J. Digital Systems Engineering 1998, Cambridge University Press, San Francisco, CA.
13. Duato J., Yalamanchili S., Ni L. Interconnection Networks: An Engineering Approach 2003, Morgan Kaufmann, Cambridge, MA.
14. Dumitra T., Kerner S., Marculescu R. Towards On-Chip Fault-Tolerant Communication. ASPDAC - Proceedings of the Asian-South Pacific Design Automation Conference 2003, 225-232.
15. Goel S., Chiu K., Marinissen E., Nguyen T., Oostdijk S. Test Infrastructure Design for the Nexperia Home Platform PNX8550 System Chip. DATE-Proceedings of the Design Automation and Test Europe Conference 2004.
16. Goossens K., van Meerbergen J., Peeters A., Wielage P. Networks on Silicon: Combining Best Efforts and Guaranteed Services. Design Automation and Test in Europe Conference 2002, 423-427.
17. Hegde R., Shanbhag N. Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise. IEEE Transactions on VLSI Systems August 2000, Vol. 8(No. 4):379-391.
18. Ho R., Mai K., Horowitz M. The Future of Wires. Proceedings of the IEEE January 2001.
19. Hu J., Marculescu R. Energy-Aware Mapping for Tile-Based NOC Architectures Under Performance Constraints. Asian-Pacific Design Automation Conference 2003.
20. Karim F., Nguyen A., Dey S. On-Chip Communication Architecture for OC-768 Network Processors. Proceedings of the 38th Design Automation Conference 2001.
21. Khailany B., et al. Imagine: Media Processing with Streams. IEEE Micro 2001, Vol. 21(No. 2):35-46.
22. Kumar S., et al. A Network on Chip Architecture and Design Methodology. VLSI on Annual Symposium, IEEE Computer Society ISVLSI 2002 2001.
23. Lackey D., Zuchowski P., Bednar T., Stout D., Gould S., Cohn J. Managing Power and Performance for Systems on Chip Design Using Voltage Islands. ICCAD - International Conference on Computer Aided Design 2002, 195-202.
24. Lieverse P., van der Wolf P., Vissers K., Deprettere E. A Methodology for Architecture Exploration of Heterogeneous Signal Processing Systems. Journal of VLSI Signal Processing for Signal, Image and Video Technology 2001, Vol. 29(No. 3):197-207.
25. Oka M., Suzuoki M. Designing and Programming the Emotion Engine. IEEE Micro November-December 1999, Vol. 19(No. 6):20-28.
26. Pham D., et al. Overview of the Architecture, Circuit Design, and Physical Implementation of a First-Generation Cell Processor. IEEE Journal of Solid-State Circuits January 2006, Vol. 41(No. 1):179-196.
27. Pinto A., Carloni L., Sangiovanni-Vincentelli A. Constraint-Driven Communication Synthesis. Design Automation Conference 2002, 195-202.
28. Skadron K., et al. Temperature-Aware Computer Systems: Opportunities and Challenges. IEEE Micro November-December 2003, Vol. 23(No. 6):52-61.
29. Sylvester D., Keutzer K. A Global Wiring Paradigm for Deep Submicron Design. IEEE Transactions on CAD/ICAS February 2000, Vol. 19(No. 2):242-252.
30. Tamhankar R., Murali S., De Micheli G. Performance Driven Reliable Link for Networks on Chip. ASPDAC - Proceedings of the Asian Pacific Conference on pesign Automation 2005, 749-754.
31. Theis T. The Future of Interconnection Technology. IBM Journal of Research and Development May 2000, Vol. 44(No. 3):379-390.
32. Waingold E., et al. Baring It All to Software: Raw Machines. IEEE Computer September 1997, Vol. 30(No. 9):86-93.
33. Walrand J., Varaiya P. High-Performance Communication Networks 2000, Morgan Kaufmann, San Francisco, CA.
34. Wolfe M. High Performance Compilers for Parallel Computing 1995, Addison-Wesley, San Francisco, CA.
35. Worm F., Ienne P., Thiran P., De Micheli G. An Adaptive Low-Power Transmission Scheme for On-Chip Networks. ISSS, Proceedings of the International Symposium on System Synthesis 2002, 92-100.
36. Zhang H., George V., Rabaey J. Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness. IEEE Transactions on VLSI Systems June 2000, Vol. 8(No. 3):264-272.
37. http://public.itrs.net/.
38. Ackland B., et al. A Single Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP. IEEE Journal of Solid-State Circuits March 2000, Vol. 35(No. 3).
39. Adriahantenana A., Greiner A. Micro-network for SoC: Implementation of a 32-Bit SPIN Network. Design Automation and Test in Europe Conference 2003, 1128-1129.
40. Agrawal A. Raw Computation. Scientific American August 1999, Vol. 281(No. 2):44-47.
41. Aldworth P. System-on-a-Chip Bus Architecture for Embedded Applications. IEEE International Conference on Computer Design 1999, 297-298.
42. Alho M., Nurmi J. Implementation for Interface Router IP for Proteo Network on Chip. Proceedings of the International Workshop on Design and Diagnostic of Electronic Circuits and Systems 2003.
43. Andriahantenaina A., Grenier A. Micronetwork for SoC: Implementation of a 32-port SPIN Network. DATE - Proceedings of Design Automation Test in Europe 2003, 1128-1129.
44. Benini L., De Micheli G. Networks on Chips: A New SoC Paradigm. IEEE Computers January 2002, 70-78.
45. Bolotin E., Cidon I., Ginosaur R., Kolodny A. QNoC: QoS Architecture and Design Process for Network on Chip. Journal of System Architecture February 2004, Vol. 50(No. 2-3):105-128.
46. Coppola M., Locatelli R., Maruccia G., Pieralisi L., Scandurra A. Spidergon: A Novel On-Chip Communication network. Proceedings of the 2004 International Symposium on System on Chip 2004, 15.
47. Cordan B. An Efficient Bus Architecture for System-on-Chip Design. IEEE Custom Integrated Circuits Conference 1999, 623-626.
48. Dall'Osso M., Biccari G., Giovannini L., Bertozzi D., Benini L. Xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for MultiProcessor SoCs. International Conference on Computer Design 2003, 536-539.
49. Dally W. Express Cubes: Improving the Performance of K-ary n-cube Inter-connection Networks. IEEE Transactions on Computers September 1991, Vol. 40(No. 9):1016-1023.
50. Dairy W., Towles B. Route Packets, Not Wires: On-Chip Interconnection Networks. DAC, Proceedings of the 38th Design Automation Conference 1991, 684-689.
51. Dally W., Towles B. Principles and Practices of Interconnection Networks 2004, Morgan Kaufmann, Upper Saddle River, NJ.
52. Duato J., Yalamanchili S., Ni L. Interconnection Networks: An Engineering Approach 2003, Morgan Kaufmann, San Francisco, CA.
53. Goossens K., Dielisssen J., Gangwal O., Pestana S., Radulescu A., Rijkema E. A Design Flow for Application Specific Networks on Chip with Guaranteed Performance to Accelerate SoC Design and Verification. DATE-Proceedings of Design Automation Test in Europe March 2005, 1182-1187.
54. Goossens K., Gangwal O., Roever J., Niranjan A. Interconnect and Memory Organization in SoCs for Advanced Set-Top Boxes and TV -Evolution, Analysis and Trends. Interconnect-Centric Design for Advanced SoC and NoC 2004, 399-423. Chapter 15, Kluwer, San Francisco, CA. J. Nurmi, H. Tenhunen, J. Isoahao, A. Jantcsh (Eds.).
55. Guerrier P., Grenier A. A Generic Architecture for On-Chip Packet-Switched Interconnections. Design Automation and Test in Europe Conference 2000, 250-256.
56. Karim F., Nguyen A., Dey S., Rao R. On-Chip Communication Architec-ture for OC-768 Network Processors. DAC-Design Automation Conference 2001, 678-683.
57. Kumar S., Jantsch A., Soininen J., Forsell M., Millberg M., Oberg J., Tiensyrj K., Hemani A. A Network on Chip Architecture and Design Methodology. Proceedings of IEEE Computer Society Annual Symposium on VLSI April 2002, 105-112.
58. Lee S.-Y., Song S.-J., Lee K., Woo J.-H., Kim S.-E., Nam B.-G., Yoo H.-J. An 800 MHz Star-Connected On-chip Network for Application to Systems on a Chip. IEEE Solid-State Circuits Conference 2003, 468-469.
59. Leiserson C. Fat-Trees: Universal Networks for Hardware-Efficient Super-computing. IEEE Transactions on Computers October 1985, Vol. 34(No. 10):892-901.
60. Murali S., De Micheli G. An Application-Specific Design Methodology for STbus Crossbar Generation. DATE - Design, Automation and Test in Europe 2005, Vol. 2:1176-1181.
61. Millberg M., Nilsson A., Thid R., Jantsch A. The Nostrum Backbone-A Communication Protocol Stack for Networks on Chip. Proceedings of the International Conference on VLSI Design 2004, 693-696.
62. Patel C., Chai S., Yalamanchili S., Shimmel D. Power Constrained Design of Multiprocessor Interconnection Networks. IEEE International Conference on Computer Design 1997, 408-416.
63. Remaklus W. On-chip Bus Structure for Custom Core Logic Design. IEEE Wescon 1998, 7-14.
64. Saastamoinen I., Alho M., Nurmi J. Buffer Implementation for Proteo Network on Chip. ISCAS - Proceedings of the International Symposium on Circuits and Systems 2003.
65. Strano G., Tiralongo S., Pistritto C. OCP/STBUS Plug-in Methodology. GSPX Conference 2004.
66. Weber W. CPU Performance Comparison: Standard Computer Bus Versus SiliconBacplane http://www.sonicsinc.com.
67. Wingard D. MicroNetwork-based integration for SOCs. Design Automation Conference 2001, 673-677.
68. Winegarden S. A Bus Architecture Centric Configurable Processor System. IEEE Custom Integrated Circuits Conference 1999, 627-630.
69. http://www.ocpip.org/.
70. http://www.sonicsinc.com.
71. http://www.silistix.com.
72. http://www.arm.com.
73. http://www.arm.com/products/CPUs/ARM7TDMI.html.
74. Bakoglu H.B. Circuits, Interconnections, and Packaging for VLSI 1990, Addison-Wesley, Norwell, MA.
75. Bashirullah R., et al. Current-Mode Signaling in Deep Submicrometer Global Interconnects. IEEE Transactions on VLSI Systems June 2003, Vol. 11(No. 3):406-417.
76. Benini L., et al. Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems. Proceedings of the Great Lakes Symposium on VLSI March 1997, 77-82.
77. Blalock T., et al. A High-Speed Sensing Scheme for 1T Dynamic RAM's Utilizing the Clamped Bit-Line Sense Amplifier. IEEE Journal of Solid-State Circuits April 1992, Vol. 27:618-625.
78. Brews J.R. Transmission Line Models for Lossy Waveguide Interconnec-tions in VLSI. IEEE Transactions on Electron Devices September 1986, Vol. ED-33(No. 9):1356-1365.
79. Cardarilli G.C., et al. Low Voltage Swing Circuits for Low Dissipation Busses. Proceedings of the International Symposium on Circuits and Systems 1997, 1868-1871.
80. Chandrakasan A.P., Brodersen R.W. Low Power Digital CMOS Design 1995, Kluwer Academic Publishers, Reading, MA.
81. Chandrakasan A., et al. Design of High-Performance Microprocessor Circuits 1999, 360. IEEE Press, Norwell, MA.
82. Chattopadhyay A., et al. High Speed Asynchronous Structures for Inter-clocking Domain Communication. International Conference on Electronics, Circuits and Systems 2002, 517-520.
83. Dally W.J. Computer Architecture is All About Interconnect. Proceedings of the IEEE International Symposium on High-Performance Computer Architecture 2002.
84. Dally W.J., Poulton J.H. Digital Systems Engineering 1998, Cambridge University Press, Piscataway, NJ.
85. Dhaou I.B., Sundarajan V., Tenhunen H., Parhi K.K. Energy Efficient Signaling in Deep Submicron CMOS Technology. Proceedings of the International Symposium on Circuit and Systems 2001, 319-324.
86. Dhaou I.B., Tenhunen H. Modeling Techniques for Energy-Efficient System-on-a-Chip Signaling. IEEE Circuits and Devices January 2003, Vol. 19(No. 1):8-17.
87. Dhaou I.B., et al. Current Mode, Low-Power, On-Chip Signaling in Deep-Submicron CMOS Technology. IEEE Transactions on Circuit and Systems-I March 2003, Vol. 50(No. 3):397-406.
88. Fetzer E.S., et al. A Fully Bypassed Six-Issue Integer Datapath and Register File on the Itanium-2 Microprocessor. IEEE Journal of Solid-State Circuits November 2002, Vol. 37(No. 11):1433-1440.
89. Golshan R., et al. A Novel Reduced Swing CMOS BUS Interface Circuit for High Speed Low Power VLSI Systems. Proceedings of the IEEE International Symposium on Circuits and Systems 1994, 351-354.
90. Goossen K.W., Hammond R.B. Modeling of Picosecond Pulse Propagation in Microstrip Interconnections on Integrated Circuits. IEEE Transactions on Microwave Theory Technology March 1989, Vol. 37(No. 3):469-478.
91. Gupta P., et al. Designing and Implementing a Fast Crossbar Scheduler. IEEE Micro January-February 1999, Vol. 19:20-28.
92. Hiraki M., et al. Data-Dependent Logic Swing Internal Bus Architecture for Ultralow-Power LSI's. IEEE Journal of Solid-State Circuits April 1995, Vol. 30:397-402.
93. Ho R., et al. Efficient On-Chip Global Interconnects. Digest of Technical Papers 2003, 271-274. June 2003.
94. Horowitz M., Dally W. How Scaling Will Change Processor Architecture. Digest of Technical Papers 2004, 132-133. February 2004.
95. http://public.itrs.net/files/2003ITRS/Home2003.htm.
96. Izumikawa M., et al. A Current Direction Sense Technique for Multiport SRAM. IEEE Journal of Solid-State Circuits April 1996, Vol. 31(No. 4):546-551.
97. Johnson H.W., Graham M. High-Speed Digital Design, A Handbook of Black Magic 1993, Prentice-Hall, Cambridge, UK.
98. Jose A.P., et al. Near Speed-of-Light On-Chip Interconnects Using Pulsed Current-Mode Signaling. Symposium on VLSI Circuits 2005, 108-111. Digest of Technical Papers.
99. Kanda K., et al. 40 Gb/s 4:1 MUX/1:4 DEMUX in 90 nm Standard CMOS. Digest of Technical Papers 2005, 152-153.
100. Kretzschmar C., et al. Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work. Proceedings of the Design Automation and Test Europe Conference (DATE) 2004, 512-517.
101. Kumar R. Interconnect and Noise Immunity Design for the Pentium 4 Processor. Intel Technology Journal 2001, Vol. 5. Ql. http://www.developer.intel.com/technology/itj/archive/2001.htm.
102. Lee K., et al. A High-Speed and Lightweight On-Chip Crossbar Scheduler for On-Chip Interconnection Networks. Proceedings of the IEEE European Solid-State Circuits Conference 2003, 453-456.
103. Lee K., et al. A Distributed Crossbar Switch Scheduler for On-Chip Net-works. Proceedings of the IEEE Custom Integrated Circuits Conference 2003, 671-674.
104. Lee K., et al. A 51 mW 1.6 GHz On-Chip Network for Low-Power Heterogeneous SoC Platform. Digest of Technical Papers 2004, 152-153. February 2004.
105. Lee K., et al. SILENT: Serialized Low Energy Transmission Coding for On-Chip Interconnection Networks. Proceedings of the International Conference on Computer Aided Design 2004, 448-451.
106. Lee K., et al. Low-Power Network-on-Chip for High-Performance SoC Design. IEEE Transactions on VLSI Systems 2006, 148-160.
107. Lewis E.T. An Analysis of Interconnect Aline Capacitance and Coupling for VLSI Circuits. Solid-State Electronics 1994, Vol. 27(No. 8/9):741-749.
108. Mehta H., et al. Some Issues in Gray Code Addressing. Proceedings of the Great Lakes Symposium on VLSI 1996, 178-181.
109. Mizuno M., et al. Elastic Interconnects: Repeater-Inserted Long Wiring Capable of Compressing and Decompressing Data. Digest of Technical Papers 2001, 346-347.
110. Moisiadis Y., et al. High Performance Level Restoration Circuits for Low-Power Reduced-Swing Interconnection Schemes. Proceedings of the International Conference on Electronics Circuits and Systems December 2000, 619-622.
111. Muttersbach J., et al. Practical Design of Globally-Asynchronous Locally-Synchronous Systems. Proceedings of the International Symposium on Advanced Research in Asynchronous Circuits and Systems 2000, 52-59.
112. Nakagome Y., et al. Sub-l-V Swing Internal Bus Architecture for Future Low-Power ULSI's. IEEE Journal of Solid-State Circuits April 1993, Vol. 28:414-419.
113. Schutt-Aine E., Kang S.M. Special Issue on Interconnection. Proceedings of the IEEE April 2001, Vol. 89, No. 4.
114. Ramprasad S., et al. A Coding Framework for Low-Power Address and Data Busses. IEEE Transactions on VLSI Systems June 1999, Vol. 7:212-221.
115. Sakurai T., Tamura K. Simple Formulas for Two- and Three-Dimensional Capacitances. IEEE Transactions on Electron Devices February 1983, Vol. ED-30(No. 2):183-185.
116. Seevinck E., et al. Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM s. IEEE Journal of Solid-State Circuits April 1991, Vol. 26:525-536.
117. Shin Y., et al. Narrow Bus Encoding for Low-Power DSP Systems. IEEE Transactions on VLSI Systems October 2001, Vol. 9:656-660.
118. Shin Y., et al. Partial Bus-Invert Coding for Power Optimization of System Level Bus. Proceedings of the International Symposium on Low Power Electronics and Design August 1998, 127-129.
119. Sinha M., et al. Current-Sensing for Crossbars. Proceedings of the International ASIC/SOC Conference 2001, 25-29.
120. Lee S.-J., et al. An 800 MHz Star-Connected On-Chip Network for Application to Systems on a Chip. Digest of Technical Papers February 2003, 468-469.
121. Lee S.-J., et al. Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications. IEEE Transactions on Circuits and Systems II June 2005, Vol. 52:308-312.
122. Lee S.-J., et al. Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme. Digest of Technical Papers 2005, 104-107. June 2005.
123. Stan M.R., et al. Bus-Invert Coding for Low-Power I/O. IEEE Transactions on VLSI Systems March 1995, Vol. 3:49-58.
124. Svensson C. Optimum Voltage Swing on On-Chip and Off-Chip Interconnect. IEEE Journal of Solid-State Circuits July 2001, Vol. 36:1108-1112.
125. Villiger T., et al. Self-Timed Ring for Globally-Asynchronous Locally-Synchronous Systems. Proceedings of the International Symposium on Asynchronous Circuits and Systems 2003, 141-150.
126. Wang H., et al. Power-Driven Design of Router Microarchitectures in On-Chip Networks. Proceedings of the IEEE/ACM International Symposium on Microarchitecture 2003, 105-116.
127. Wang H., et al. A Technology-Aware Energy-Oriented Topology Exploration for On-Chip Networks. Proceedings of the Design, Automation and Test in Europe Conference 2005, 1238-1243.
128. Wijetunga P., et al. High-Performance Crossbar Design for System-on-Chip. Proceedings of the IEEE International Workshop on System-on-Chip for Real-Time Applications 2003, 138-143.
129. Worm F., et al. A Robust Self-Calibrating Transmission Scheme for On-Chip Networks. IEEE Transactions on VLSI Systems January 2005, Vol. 13:126-139.
130. Yamauchi H., et al. An Asymptotically Zero Power Charge-Recycling Bus Architecture for Battery-Operated Ultrahigh Data Rate ULSI's. IEEE Journal of Solid-State Circuits April 1995, Vol. 30:423-431.
131. Zhang H., et al. Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness. IEEE Transactions on VLSI Systems June 2000, Vol. 8:264-272.
132. Zhou H., Wang D.F. Global Routing with Crosstalk Constraints. Proceeding of the 1998 Design and Automation Conference 35th DAC 1998, 374-377.
133. Chen Z., Koren I. Crosstalk Minimization in Three-Layer HVH Channel Routing. Proceeding of the IEEE International Symposium on Defect and Fault Tolerance in VLSI System 1991, 38-42.
134. Shepard K.L. Design Methodologies for Noise in Digital Integrated Circuits. Proceedings of the Design Automation Conference 1998, 94-99.
135. Stohr T., Alt H., Hetzel A., Koehl J. Analysis, Reduction and Avoidance of Crosstalk on VLSI Chips. Proceedings of the International Symposiumm Physical Design 1998, 211-218.
136. Rahmat K., Neves J., Lee J. Methods for Calculating Coupling Noise in Early Design: a Comparative Analysis. Proceedings of the International Conference on Computer Design VLSI in Computers and Processors 1998, 76-81.
137. Kawaguchi H., Sakurai T. Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. Proceedings of the Asian and South Pacific Design Automation Conference 1998, 35-43.
138. Vittal A., Marek-Sadowska M. Crosstalk Reduction for VLSI. IEEE Transaction on Computer-Aided Design of Integrated Circuits and Systems 1997, Vol. 16(No. 3):290-298.
139. Ho T.Y., Chang Y.W., Chen S.J., Lee D.T. Crosstalk- and Performance-Driven Multilevel Full-Chip Routing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems June 2005, Vol. 24(No. 6):869-878.
140. Pullini A., Angiolini F., Bertozzi D., Benini L. Fault Tolerance Overhead in Network-on-Chip Flow Control Schemes. Proceedings of the 18th Annual Symposium on Integrated Circuits and System Design (SBCCI2005) 2005, 224-229.
141. Pradhan D. Fault Tolerant Computing: Theory and Techniques 1986, Prentice Hall, Englewood Cliffs, NJ.
142. Das D., Touba N. Weight-Based Codes and their Applications to Concurrent Error Detection of Multilevel Circuits. Proceedings of the VLSI Test Symposium 1999, 370-376.
143. Favalli M., Metra C. Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors. Proceedings of the DATE March 2001, 290-296.
144. Ball H., Hardy F. Effects and Detection of Intermittent Failures in Digital Systems. Proceedings of the Fall Joint Computer Conference, American Federation of Information Processing Societies Conference 1969, 329-335.
145. Iyer R., Rosetti D. A Statistical Load Dependency of CPU Errors at SLAC. Proceedings of the Fault Tolerance Computing Systems FTCS 1982, 363-372.
146. Maheshwari A., Burleson W., Tessier R. Trading Off Transient Fault Tolerance and Power Consumption in Deep Submicron (DSM) VLSI Circuits. IEEE Transaction on Very Large Scale Integration (VLSI) Systems March 2004, Vol. 12(No. 3):299-311.
147. Nicolaidis M. IP for embedded robustness. Proceedings of the DATE 2002, 240-241.
148. Wong H.P., Frank D.J., Solomon P.M., Wann C.H.J., Welser J.J. Nanoscale CMOS. Proceedings of the IEEE April 1999, 537-570. Vol. 87, No. 4.
149. Dally W.J., Towles B. Principles and Practices of Interconnection Networks 2004, Morgan Kaufmann, Englewood Cliffs, NJ.
150. Bai G., Hajj I.N. Simultaneous Switching Noise and Resonance Analysis of on-Chip Power Distribution Network. Proceedings of the IEEE International Symposium on Quality Electronic Design 2002, 163-168.
151. Chen C.L., Curran B.W. Switching Codes for Delta-I Noise Reduction. IEEE Transaction on Computers September 1996, 1017-1021.
152. Moore G.E. No Exponential is Forever: But 'Forever' Can Be Delayed!. Proceedings of the ISSCC 2003, Vol. 1:20-23.
153. Hedge R., Shanbhag N.R. Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise. IEEE Transactions on - VLSI Systems August 2000, Vol. 8(No. 4):379-391.
154. Bertozzi D., Benini L., De Micheli G. Low Power Error Resilient Encoding for on-Chip Data Buses. Proceedings of the DATE 2002, 102-109.
155. Bertozzi D., Benini L., Ricco B. Energy-Efficient and Reliable Low-swing Signaling for On-Chip Buses Based on Redundant Coding 2002, ISLPED I-93-I-96.
156. Bertozzi D., Benini L., De Micheli G. Error Control Schemes for On-Chip Communication Links: The Energy-Reliability Tradeoff. IEEE Transaction on CAD of Integrated Circuits and Systems June 2005, Vol. 24(No. 6):818-831.
157. Sridhara S.R., Shanbhag N.R. Coding for System-on-Chip Networks: A Unified Framework. IEEE Transactions on VLSI Systems June 2005, Vol. 13(No. 6):655-667.
158. Li L., Vijaykrishnan N., Kandemir M., Irwin MJ. Adaptive Error Protection for Energy Efficiency. International Conference on Computer Aided Design (ICCAD 2003) 2003, 2-7.
159. Vellanki P., Banerjee N., Chatha K.S. Quality-of-Service and Error Control Techniques for Mesh-Based Network-on-Chip Architectures. INTEGRATION, the VLSI Journal 2005, Vol. 38:353-382.
160. Jantsch A., Lauter R., Vitkowski A. Power Analysis of Link Level and End-to-End Data Protection in Networks on Chip. International Symposium on Circuits and Systems 2005, Vol. 2:1770-1773.
161. Zimmer H., Jantsch A. A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip. CODES ISSS 2003 2003, 188-193.
162. Dumitras T., Kerner S., Marculescu R. Towards On-Chip Fault-Tolerant Communication. Proceedings of the ASP-DAC 2003 2003, 225-232.
163. Marculescu R. Networks-on-Chip: The Quest for On-Chip Fault-Tolerant Communication. Proceedings of the IEEE Computer Society Annual Symposium on VLSI ISVLSI'03 2003, 8-12.
164. Lin S., Costello D.J. Error Control Coding: Fundamentals and Applications 1983, Prentice-Hall, San Francisco, CA.
165. Roman S. Introduction to Coding and Information Theory 1997, Springer Verlag, Englewood Cliffs, NJ.
166. Stueber G.L. Principles of Mobile Communication 2001, Kluwer Academic Publishers, Berlin, Germany. 2nd edition.
167. Koopman P., Chakravarty T. Cyclic redundancy code (CRC) polynomial selection for embedded systems. The International Conference on Dependable Systems and Networks 2004, 1-10.
168. Peterson W.W., Brown D.T. Cyclic Codes for Error Detection. Proceedings of the IRE January 1961, 228-235.
169. Nordqvist U., Henrikson T., Liu D. Configurable CRC Generator. Proceedings. DDECS April 2002, 192-199.
170. Sobski A., Albicki A. Partitioned and Parallel Cyclic Redundancy Checking. Proceedings of the 36th Symposium Circuits and Systems August 1993, Vol. 1:538-541.
171. Mello A., Moeller L., Calazans N., Moraes F. MultiNoC: A Multiprocessing System Enabled by a Network on Chip. Design, Automation and Test in Europe (DATE'05) 2005, Vol. 3:234-239.
172. Bolotin E., Cidon I., Ginosar R., Kolodny A. QNoC: QoS Architecture and Design Process for Network on Chip. Special issue on Networks on Chip, The Journal of Systems Architecture February 2004, Vol. 50(No. 2-3):105-128.
173. Rijpkema E., Goossens K., Radulescu A., Dielissen J., van Meerbergen J., Wielage P., Waterlander E. Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. IEE Proceedings: Computers and Digital Techniques 2003, 294-302. Vol. 150, No. 5.
174. Rossi D., van Dijk V.E.S., Kleihorst R.P., Nieuwland A.H., Metra C. Coding Scheme for Low Power Consumption Fault Tolerant Bus. IEEE Proceedings of the International On Line Testing Workshop 2002, 8-12.
175. Rossi D., van Dijk V.E.S., Kleihorst R.P., Nieuwland A.K., Metra C. Power Consumption of Fault-Tolerant Bus: The Active Elements. Proceedings of the IEEE International On Line Testing Symposium 2003, 61-67.
176. Rossi D., Muccio A., Nieuwland A.K., Katoch A., Metra C. Impact of ECCs on Simultaneously Switching Output Noise for On-Chip Busses of High Reliability Systems. Proceedings of the 10th IEEE International On-Line Testing Symposium 2004, 135-140.
177. Rossi D., Nieuwland A.K., Katoch A., Metra C. Exploiting ECC Redundancy to Minimize Crosstalk Impact. IEEE Design and Test of Computers 2005, 59-70.
178. Rossi D., Nieuwland A.K., Katoch A., Metra C. New ECC for Crosstalk Impact Minimization. IEEE Design and Test of Computers 2005, 340-348.
179. Zhang H., George V., Rabaey J.M. Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 2000, Vol. 8(No. 3):264-272.
180. Sotiriadis P.P. Interconnect Modelling and Optimization in Deep Submicron Technologies. Ph.D. dissertation May 2002, Massachusetts Institute of Technology, Norwell, MA.
181. Duan C., Tirumala A., Khatri S.P. Analysis and Avoidance of Crosstalk in On-Chip Buses. Proceedings of the Hot Interconnects 2001, 133-138.
182. Victor B., Keutzer K. emphBus Encoding to Prevent Crosstalk Delay. Proceedings of the ICCAD'01 2001, 57-63.
183. Sridhara S.R., Ahmed A., Shanbhag N.R. Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. Proceedings of the ICCAD'04 2004, 12-17.
184. Ramprasad S., Shanbhag N.R., Hajj I.N. A Coding Framework for Low-Power Address and Data Busses. IEEE Transactions on VLSI Systems June 1999, Vol. 7(No. 2):212-221.
185. Stan M.R., Burleson W.R Bus-Invert Coding for Low-Power I/O. IEEE Transactions on VLSI Systems March 1995, Vol. 3(No. 1):49-58.
186. Kim K., Baek K., Shanbhag N., Liu C., Kang S. Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. Proceedings of the ICCAD'00 2000, 318-321.
187. Zhang Y., Lach J., Skadron K., Stan M.R. Odd/Even Bus Invert With Two-Phase Transfer for Buses with Coupling. Proceedings of the ISLPED'02 2002, 80-83.
188. Austin T., Blaauw D., Mudge T., Flautner K. Making Typical Silicon Matter with Razor. IEEE Computer March 2004, Vol. 37(No. 3):57-65.
189. Worm F., Ienne P., Thiran P., De Micheli G. Transmission Scheme for On-Chip Networks. IEEE Transactions on Very Large Scale Integration (VLSI) Systems January 2005, Vol. 13(No. 1):126-139.
190. Worm F., Thiran P., De Micheli G., Ienne P. Self-Calibrating Networks-on-Chip. Proceedings of the IEEE International Symposium on Circuits and Systems (2005) 2005, 2361-2364.
191. Worm F., Thiran P., Ienne P. Soft Self-Synchronising Codes for Self-Calibrating Communication. Proceedings of the International Conference on CAD November 2004, 440-447.
192. Morgenshtein A., Bolotin E., Cidon I., Kolodny A., Ginosar R. Micro-Modem -Reliability Solution for NoC Communications. ICECS 2004, 483-486.
193. Millberg M. The Nostrum Protocol Stack and Suggested Services Provided by the Nostrum Backbone. Internal Report in Electronic System Design TRITA-IMIT-LECSR02:01 2003, LECS, IMIT, KTH, Cambridge.
194. Lee S.J., Kim K., Kim H., Cho N., Yoo H.J. Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme. International Symposium on VLSI Circuits (VLSI) June 2005, 104-107.
195. Millberg M., Nilsson E., Thid R., Jantsch A. The Nostrum Back-bone A Communication Protocol Stack for Networks-on-Chip. Proceedings of the International Conference on VLSI Design January 2004, 693-696.
196. Karp R., et al. Randomized Rumor Spreading. Proceedings of the IEEE Symposium on Foundations of Computer Science 2000, 565-574.
197. Birman K., et al. Bimodal Multicast. ACM Transactions on Computer Systems 1999, Vol. 17(No. 2):41-88.
198. Pirretti M., Link G.M., Brooks R., Vijaykrishnan N., Kandemir M., Irwin M.J. Fault Tolerant Algorithm for Network-on-Chip Interconnect. Proceedings of the IEEE Computer Society Annual Symposium on VLSI Emerging Trends in VLSI Systems Design ISVLSI'04 2004, 46-51.
199. Murali S., Theocharides T., Vijaykrishnan N., Irwin M.J., Benini L., De Micheli G. Analysis of Error Recovery Schemes for Networks on Chips. IEEE Design and Test of Computers 2005, 434-442.
200. Berkeley Predictive Technology Model http://www.
201. Stergiou S., Angiolini F., Carta S., Raffo L., Bertozzi D., Benini L., De Micheli G. Xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips. Proceedings of the Conference on Design, Automation and Test in Europe March 2005, Vol. 2:1188-1193.
202. Tamhankar R.R., Murali S., De Micheli G. Performance Driven Reliable Link Design for Networks on Chips. Proceedings of the ASP-DAC'05 2005, 749-754.
203. Yeo E., Augsburger S.A., Davis W.R., Nikolic B. A 500-Mb/s Soft-Output Viterbi Decoder. IEEE Journal of Solid-State Circuits July 2003, Vol. 38(No. 7):1234-1241.
204. Angiolini F., Bertozzi D., Raffo L., Meloni P., Carta S., Benini L. Xpipes Network on Chip: A Synthesis Perspective. Parallel Computing Minisymposium 12-16 September 2005, Malaga (Spain).
205. Nguyen G.D. Error-Detection Codes: Algorithms and Fast Implementation. IEEE Transactions on Computers January 2005, Vol. 54(No. 1):1-11.
206. Albertango G., Sisto R. Parallel CRC Generation. IEEE Micro October 1990, Vol. 10(No. 5):63-71.
207. Pei T.B., Zukowski C. High-Speed Parallel CRC Cicuits in VLSI. IEEE Transactions on Communications 1992, Vol. 40(No. 4):653-657.
208. Hobson R.F., Cheung K.L A High-Performance CMOS 32-Bit Parallel CRC Engine. IEEE Journal Solid State Circuits February 1999, Vol. 34(No. 2):233-235.
209. Nair R., Ryan G., Farzaneh F. A Symbol Based Algorithm for Implementation of Cyclic Redundancy Check (CRC). Proceedings of the VHDL International Users' Forum 1997, 82-87.
210. http://www.st.com/stonline/prodpres/dedicate/soc/cores/stbus.htm.
211. Benini L., De Micheli G. Networks on Chip: A New Paradigm for Component-Based MPSoC Design. Multiprocessors Systems on Chips 2004, 49-80. Morgan Kaufmann, Stockholm, Sweden. A. Jerrraya, W. Wolf (Eds.).
212. Chao H.J., Lam C.H., Guo X. A Fast Arbitration Scheme for Terabit Packet Switches. Proceedings of the IEEE Global Telecommunications Conference 1999, 1236-1243.
213. Mckeown N., Varaiya P., Warland J. The iSLIP Scheduling Algorithm for Input-Queued Switch. IEEE Transactions on Networks 1999, 188-201.
214. Chao H.J., Park J.S. Centralized Contention Resolution Schemes for a Larger-Capacity Optical ATM Switch. Proceedings of the IEEE ATM Workshop 1998, 11-16.
215. Shin E.S., Mooney V.J., Riley G.F. Round-Robin Arbiter Design and Generation. Proceedings of the 15th International Symposium on System Synthesis (ISSS '02) 2002, 243-248.
216. AMBA AHB Specification, Rev.2.0, ARM, 1999.
217. Castagnoli G., Brauer S., Herrmann M. Optimization of Cyclic Redundancy-Check Codes with 24 and 32 Parity Bits. IEEE Transactions on Communications June 1993, Vol. 41(No. 6):883-892.
218. Glaise R.J., Jacquart X. Fast CRC Calculation. 1993 IEEE International Conference on Computer Design: VLSI in Computers and Processors 1993, 602-605.
219. Ramabadran T.V., Gaitonde S.S. A Tutorial on CRC Computations. IEEE Micro August 1988, Vol. 8(No. 4):62-75.
220. Adriahantenaina A., Charlery H., Greiner A., Mortiez L., Zeferino C.A. SPIN: A Scalable, Packet Switched, On-Chip Micro-Network. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2003.
221. http://www.arm.com/products/solutions/axi_spec.html.
222. ATM Forum ATM User-Network Interface Specification July 1994, Prentice Hall, San Francisco, CA, Version 3.1.
223. Aurrecoechea C., Campbell A.T., Hauw L. A Survey of QoS Architec- tures. Multimedia Systems 1998, Vol. 6(No. 3):138-151.
224. Bertozzi D., Benini L. Xpipes: A Network-on-Chip Architecture for Gigascale Systems-on-Chip. IEEE Circuits and Systems Magazine 2004, Vol. 4(No. 2):18-31.
225. Bjerregaard T. The MANGO Clockless Network-on-Chip: Concepts and Implementation. Ph.D. thesis 2006, Informatics and Mathematical Modelling, Technical University of Denmark, DTU, Upper Saddle River, NJ.
226. Bjerregaard T., Mahadevan S., Grøndahl R., Sparsø J. An OCP Compliant Adapter for GALS-Based SoC Design Using the MANGO Network-on-Chip. Proceedings of the International Symposium on Systems on Chip (SoC) 2005.
227. Bjerregaard T., Sparsø J. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005, 1226-1231.
228. Bjerregaard T., Sparsø J. Scheduling Discipline for Latency and Band-width Guarantees in Asynchronous Network-on-Chip. Proceedings of the International Symposium on Asynchronous Circuits and Systems (ASYNC) March 2005, 34-43.
229. Bjerregaard T., Sparsø J. Implementation of Guaranteed Services in the MANGO Clockless Network-on-Chip. IEE Proceedings: Computers and Digital Techniques 2006.
230. Bodlaender H.L., van Leeuwen J., Tan R., Thilikos D. On Interval Routing Schemes and Treewidth. Information and Computation November 25, 1997, Vol. 139(No. 1):92-109.
231. Bolotin E., Cidon I., Ginosar R., Kolodny A. Cost considerations in Network on Chip. Integration, the VLSI Journal October 2004, Vol. 38(No. 1):19-42.
232. Bolotin E., Cidon I., Ginosar R., Kolodny A. QNoC: QoS Architecture and Design Process for Network on Chip. Journal of Systems Architecture February 2004, Vol. 50(No. 2-3):105-128. Special issue on Networks on Chip.
233. Bolotin E., Cidon I., Ginosar R., Kolodny A. Efficient Routing in Irregular Topology Noes. Technion, CCIT Report September 2005, Vol. 554(No. 5).
234. Borgonovo F., Fratta L., Bannister J.A. On the Design of Optical Deflection-Routing Networks. Proceedings of the Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM) 1994, 120-129.
235. Braden R., Clark D., Shenker S. Integrated Services in the Internet Architecture: An Overview. Internet Drafts June 1996, RFC 1633, Available at. http://www.rfc_archive.org/getrfc.phprfc=1633.
236. Brassil J., Cruz R.L. Bounds on Maximum Delay in Networks with Deflection Routing. IEEE Transactions on Parallel and Distributed Systems 1995, Vol. 6(No. 7):724-732.
237. Cidon I., Guérin R., Khamisy A. On Protective Buffer Policies. IEEE/ACM Transactions on Networking 1994, Vol. 2(No. 3):240-246.
238. Cidon I., Jaffe F.M., Sidi M. Local Distributed Deadlock Detection by Cycle Detection and Clustering. IEEE Transactions on Software Engineering 1987, Vol. 13(No. 1):3-14.
239. Cidon I., Jaffe J.M., Sidi M. Distributed Store-and-Forward Deadlock Detection and Resolution Algorithms. IEEE Transactions on Communication 1987, Vol. 35(No. 11):1139-1145.
240. Cidon I., Keidar I. Zooming in on Network on Chip Architectures. Technion, CCIT Report December 2005, Vol. 565(No. 5).
241. Ciordaş C., Basten T., Rǎdulescu A., Goossens K., van Meerbergen J. An Event-Based Network-on-Chip Monitoring Service. ACM Transactions on Design Automation of Electronic Systems October 2005, Vol. 10(No. 4):702-723. HLDVT'04 Special Issue on Validation of Large Systems.
242. Culler D.J., Singh J.P., Gupta A. Parallel Computer Architecture: A Hardware/Software Approach 1999, Morgan Kaufmann Publishers.
243. Dally W., Towles B. Principles and Practices of Interconnection Networks 2003, Morgan Kaufmann Publishers Inc., San Francisco, CA.
244. Dally W.J. Express Cubes: Improving the Performance of k-ary n-cube Interconnection Networks. IEEE Transactions on Computers September 1991, Vol. 40(No. 9):1016-1023.
245. Dally W.J. Virtual-Channel Flow Control. IEEE Transactions on Parallel and Distributed Systems March 1992, Vol. 3(No. 2):194-205.
246. Dally W.J., Aoki H. Adaptive routing using virtual channels. Technical Report September 1990, Laboratory for Computer Science, MIT, San Francisco, CA, USA.
247. Dally W.J., Aoki H. Deadlock-Free Adaptive Routing in Multicomputer Networks Using Virtual Channels. IEEE Transactions on Parallel and Distributed Systems April 1993, Vol. 4(No. 4):466-475.
248. Dally W.J., Seitz C.L. Deadlock-Free Message Routing in Multiprocessor Interconnection Networks. IEEE Transactions on Computers May 1987, Vol. 36(No. 5):547-553.
249. Dally W.J., Towles B. Route Packets, Not Wires: On-Chip Interconnection Networks. Proceedings of the Design Automation Conference (DAC) 2001, 684-689.
250. DeHon A., Robust high-speed network design for large-scale. Multiprocessing, A.I. Technical report 1445 September 1993, Massachusetts Institute of Technology, Artificial Intelligence Laboratory, Cambridge, Massachusetts.
251. Dielissen J., Radulescu A., Goossens K., Rijpkema E. Concepts and Implementation of the Philips Network-on-Chip. Workshop on IP-Based System-on-Chip Design November 2003.
252. Duato J., Yalamanchili S., Ni L. Interconnection Networks - An Engineering Approach 2003, Morgan Kaufmann, Cambridge, MA.
253. Dumitras T., Marculescu R. On-Chip Stochastic Communication. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2003.
254. Feige U., Raghavan P. Exact Analysis of Hot-Potato Routing. Proceedings of the Annual Symposium on Foundations of Computer Science October 1992, 553-562.
255. Fleury E., Fraigniaud P. A General Theory for Deadlock Avoidance in Wormhole-Routed Networks. IEEE Transactions on Parallel and Distributed Systems July 1998, Vol. 9(No. 7):626-638.
256. Gangwal O.P., Radulescu A., Goossens K., Pestana S.González, Rijpkema E. Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Æthereal Network on Chip. Philips Research Book Series 2005, 1-36. Chapter 1, Springer, San Francisco, CA. P. van der Stok (Ed.).
257. Gerla M., Kleinrock L. Flow Control: A Comparative Survey. IEEE Transactions on Communications April 1980, Vol. COM-28(No. 4):553-574.
258. Gindin R., Cidon I., Keidar I. NoC architecture for future fpgas, Department of EE. CCIT Report 579 March 2006, Technion, Berlin, Germany.
259. Glass C.J., Ni L.M. The Turn Model for Adaptive Routing. InternationalSymposium on Computer Architecture May 1992, 278-287.
260. Glass C.J., Ni L.M. The Turn Model for Adaptive Routing. Journal ofthe ACM September 1994, Vol. 41(No. 5):874-902.
261. Pestana S.Gonzalez, Goossens K., Radulescu A., Thid R. Frameworkand performance metric definitions: A first step towards network-on-chip benchmarking January 2006, Technical Note 2006/00003, Philips Research.
262. Goossens K., Dielissen J., Gangwal O.P., Pestana S.Gonzalez, Radulescu A., Rijpkema E. A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SOC Design and Verification. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005, 1182-1187.
263. Goossens K., Dielissen J., Rǎdulescu A. The Æthereal Network on Chip: Concepts, Architectures, and Implementations. IEEE Design and Test of Computers September-October 2005, Vol. 22(No. 5):21-31.
264. Goossens K., Dielissen J., van Meerbergen J., Poplavko P., Radulescu A., Rijpkema E., Waterlander E., Wielage P. Guaranteeing the quality of Services in Networks on Chip. Networks on Chip 2003, 61-82. Chapter 4, Kluwer. A. Jantsch, H. Tenhunen (Eds.).
265. Goossens K., Gangwal O.P., Rover J., Niranjan A.P. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV - Evolution, Analysis, and Trends. Interconnect-Centric Design for Advanced SoCand NoC 2004, 399-423. Chapter 15, Kluwer, Norwell, MA. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch (Eds.).
266. Goossens K., van Meerbergen J., Peeters A., Wielage P. Networks on Silicon: Combining Best-Effort and Guaranteed Services. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2002, 423-425.
267. Greenberg A.G., Madras N. How Fair Is Fair Queueing. Journal of the ACM 1992, 568-598.
268. Guerrier P. Un Réseau D'Interconnexion pour Systémes Intégrés. Ph.D.thesis March 2000, Université Paris VI, Norwell, MA.
269. Guerrier P., Greiner A. A Generic Architecture for On-Chip Packet-Switched Interconnections. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2000, 250-256.
270. Günther K.D. Prevention of Deadlocks in Packet-Switched Data Transport System. IEEE Transactions on Communications April 1981, Vol. 29:512-524.
271. Guz Z., Walter I., Bolotin E., Cidon I., Ginosar R., Kolodny A. Efficient Link Capacity and QoS Design for Wormhole Network-on-Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005, 9-14.
272. Hansson A., Goossens K., Rǎdulescu A. UMARS: A unified approach to mapping and routing on a combined guaranteed service and best-effort network-on-chip architecture. Technical Report 2005/00340 April 2005, Philips Research, Paris, France.
273. Hansson A., Goossens K., Radulescu A. A Unified Approach to Constrained Mapping and Routing on Network-on-Chip Architectures. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) September 2005, 75-80.
274. Hansson A., Goossens K., Radulescu A. Analysis of message-dependent deadlock in network-based systems on chip. Technical Report 2006/00230 March 2006, Philips Research.
275. Harmanci M., Escudero N., Leblebici Y., Ienne P. Quantitative Modelling and Comparison of Communication Schemes to Guarantee Quality-of-Service in Networks-on-Chip. Proceedings of the InternationalSymposium on Circuits and Systems (ISCAS) 2005, 1782-1785.
276. Hu J., Marculescu R. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2003, 688-693.
277. Hu J., Marculescu R. DyAD - Smart Routing for Networks on Chip. Proceedings of the Design Automation Conference (DAC) June 2004.
278. Hu J., Marculescu R. Energy- and Performance-Aware Mapping for Regular NoC Architectures. IEEE Transactions on CAD of Integrated Circuits and Systems April 2005, Vol. 24(No. 4):551-562.
279. Humblet P., Bhargava A., Hluchyj M.G. Ballot Theorems Applied to the Transient analysis of nD/D/1 Queues. IEEE/ACM Transactions on Networking 1993, Vol. 1(No. 1):81-95.
280. Jalabert A., Murali S., Benini L., De Micheli G. XpipesCompiler: A Tool for Instantiating Application Specific Networks on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2004.
281. Kavaldjiev N., Smit G.J.M., Jansen P.G. A Virtual Channel Router for On-Chip Networks. Proceedings of the International SOC Conference (SoCC) September 2004.
282. Kung H.T., Blackwell T., Chapman A. Credit-Based Flow Control for ATM Networks: Credit Update Protocol, Adaptive Credit Allocation and Statistical Multiplexing. SIGCOMM 1994, 101-114.
283. Laffely A., Liang J., Jain P., Weng N., Burleson W., Tessier R. Adaptive Systems on a Chip (aSoC) for Low-Power Signal Processing. Proceedings of the Asilomar Conference on Signals, Systems, and Computers 2001.
284. Laffely A.J. An Interconnect-Centric Approach for Adapting Voltage and Frequency in Heterogeneous System-on-a-Chip. Ph.D. thesis 2003, University of Massachusetts, Eindhoven, The Netherlands.
285. Lee K., Lee S.-J., Yoo H.-J. A Distributed Crossbar Switch Scheduler for On-Chip Networks. Proceedings of the Custom Integrated Circuits Conference 2003.
286. Lee K., Lee S.-J., Yoo H.-J. A High-Speed and Lightweight On-Chip Crossbar Switch Scheduler for On-Chip Interconnection Networks. Proceedings of the International Conference on European Solid-State Circuits 2003.
287. Leiserson C. Fat-Trees: Universal Networks for Hardware-efficient supercomputing. IEEE Transactions on Computers October 1985, Vol. C-34(No.10):892-901.
288. Linder D.H., Harden J.C. An adaptive and Fault Tolerant Wormhole Routing Strategy for k-ary n-cubes. IEEE Transactions on Computers January 1991, Vol. 40(No. 1):2-12.
289. Litman A., Moran-Schein S. Fast, Minimal, and Oblivious Routing Algorithms on the mesh with bounded Queues. Journal of Interconnection Networks 2001, Vol. 2(No. 4):445-469.
290. López P., Martínez J.M., Duato J. A Very Efficient Distributed Deadlock Detection Mechanism for Wormhole Networks. Proceedings of the International Symposium on High-Performance Computer Architecture (HPCA) February 1998, 57-66.
291. Maxemchuk N.F. Routing in the Manhattan Street Network. IEEE Transactions on Communication May 1987, Vol. COM-35(No. 2-3):503-512.
292. McDysan D.E., Spohn D.L. ATM: Theory and Application 1994, McGraw-Hill, Inc., Amherst, MA.
293. Millberg M., Nilsson E., Thid R., Jantsch A. Guaranteed Bandwidth Using Looped Containers in Temporally Disjoint Networks within the Nostrum Network on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2004.
294. Millberg M., Nilsson E., Thid R., Kumar S., Jantsch A. The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. Proceedings of the International Conference on VLSI Design 2004, 693-696.
295. Mohapatra P. Wormhole Routing Techniques for Directly Connected Multicomputer Systems. ACM Computing Surveys 1998, Vol. 30(No, 3):374-410.
296. Murali S., Benini L., de Micheli G. Mapping and Physical Planning of Networks on Chip Architectures with Quality of Service Guarantees. Proceedings of the Design Automation Conference, Asia and South Pacific (ASPDAC) 2005.
297. Murali S., Coenen M., Radulescu A., Goossens K., De Micheli G. A Methodology for Mapping Multiple Use-Cases on to Networks on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2006, 118-123.
298. Murali S., De Micheli G. SUNMAP: A Tool for Automatic Topology Selection and Generation for NOCs. Proceedings of the Design Automation Conference (DAC) June 2003.
299. Ni L.M., McKinley P.K. A Survey of Wormhole Routing Techniquesin Direct Networks. IEEE Computer February 1993, Vol. 26(No. 2):62-76.
300. Nichols K., Blake S., Baker F., Black D. Definition of the Differentiated Services Field (DS Field) in the IPv4 and IPv6 Headers. The RFC archive - RFC 2474 December 1998, 1126-1127. Available athttp://www.rfc_archive.org/getrfc.php?rfc=2474.
301. Nilsson E., Millberg M., Öberg J., Jantsch A. Load Distribution with the Proximity Congestion Awareness in a Network on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) 2003.
302. Nollet V., Marescaux T., Avasare P., Verkest D., Mignolet J.-Y. CentralizedRun-Time Resource Management in a Network-on-Chip Containing Reconfigurable Hardware Tiles. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005, 234-239.
303. Nollet V., Marescaux T., Verkest D. Operating-System Controlled Network-on-Chip. Proceedings of the Design, Automation conference(DAC) June2005, 256-259.
304. OCP International Partnership Open Core Protocol Specification 2001, 1342-1347. Available athttp://www.ocpip.org.
305. Ogras U.Y., Hu J., Marculescu R. Key Research Problems in NoC Design: A Holistic Perspective. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) September 2005.
306. Pande P., Grecu C., Ivanov, Saleh R. Design of a Switch for Network on Chip Applications. Proceedings of the International Symposium on Circuits and Systems (ISCAS) 2003.
307. Rijpkema E., Goossens K., Rǎdulescu A., Dielissen J., van Meerbergen J., Wielage P., Waterlander E. Trade Offs in the Design of a Router withBoth Guaranteed and Best-Effort Services for Networks on Chip. IEE Proceedings: Computers and Digital Technique September 2003, 294-302. No. 5.
308. Rijpkema E., Goossens K., Wielage P. A Router Architecture for Networks on Silicon. Proceedings of Progress 2001, 2nd Workshop on Embedded Systems October 2001.
309. Radulescu A., Dielissen J., Pestana S.Gonzalez, Gangwal O.P., Rijpkema E., Wielage P., Goossens K. An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Programming. IEEE Transactions on CAD of Integrated Circuits and Systems January 2005, Vol. 24(No. 1):4-17.
310. Radulescu A., Goossens K. Communication Services for Networks on Chip. Domain-Specific Processors: Systems, Architectures, Modeling, and Simulation 2004, 193-213. Marcel Dekker, New York, USA. S.S. Bhattacharyya, E.F. Deprettere, J. Teich (Eds.).
311. Signenza-Tortosa D., Nurmi J. Proteo: A New Approach to Network-on-Chip. Proceedings of the IAS TED International Conference on Communication Systems and Networks (CSN '02) September 9-12, 2002.
312. Seo D., Ali A., Lim W.-T., Rafique N., Thottethodi M. Near-Optimal Worst-Case Throughput Routing for Two-Dimensional Mesh Networks. International Symposium on Computer Architecture 2005, 432-443.
313. Shang L., Peh L.-S., Jha N.K. Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks. IEEE Computer Society HPCA '03: Proceedings of the 9th International Symposium on High-Performance Computer Architecture 2003, 91.
314. Shoemaker D. An Optimized Hardware Architecture and Communication Protocol for Scheduled Communication. Ph.D. thesis May 1997, Electrical Engineering and Computer Science Department, Massachusetts Institute of Technology, New York.
315. Shurbanov V., Avresky D., Mehra P., Watson W. Flow Control in Server-net Clusters. The Journal of Supercomputing June 2002, Vol. 22(No. 2):161-173.
316. Song Y.H., Pinkston T.M. A Progressive Approach to Handling Message-Dependent Deadlock in Parallel Computer Systems. IEEE Transactions on Parallel and Distributed Systems 2003, Vol. 14:259-275.
317. Steenhof F., Duque H., Nilsson B., Goossens K., Llopis R.Peset Networks on Chips for High-End Consumer-Electronics TV System Architectures. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2006, 148-153.
318. Stravers P., Hoogerbrugge J. Homogeneous Multiprocessing and the Future of Silicon Design Paradigms. International Symposium on Technology, Systems, and Applications Proceedings 2001, 184-187.
319. Tanenbaum A.S. Computer Networks 1996, Prentice-Hall, Cambridge, MA.
320. van den Brand J.W., Ciordaş C., Basten T. Runtime Networks-on-Chip Performance Monitoring. Technical Report 2006/00218 March 2006, Philips Research, Upper Saddle River, NJ.
321. Waingold E., Taylor M., Srikrishna D., Sarkar V., Lee W., Lee V., Kim J., Frank M., Finch P., Barua R., Babb J., Amarasinghe S., Agarwal A. Baring It All to Software: Raw Machines. IEEE Computer September 1997, Vol. 30(No. 9):86-93.
322. Walter I.Z. Quality of Service in Network-on-Chip. Masters thesis August 2005, Tech-nion, Israel Institute of Technology, Eindhoven, The Nertherlands.
323. Weber W.-D., Chou J., Swarbrick I., Wingard D. A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005.
324. Wiklund D. Development and Performance Evaluation of Networks on Chip. Ph.D. thesis 2005, Department of Electrical Engineering, Linkoping University, Haifa, Israel.
325. Wolkotte P.T., Smit G.J., Rauwerda G.K., Smit L.T. An Energy-Efficient Reconfigurable Circuit Switched Network-on-Chip. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS) April 2005.
326. Ye T.T, Benini L., De Micheli G. Packetization and Routing Analysis of On-Chip Multiprocessor Networks. Journal of Systems Architecture February 2004, Vol. 50(No. 2-3):81-104. Special issue on Networks on Chip.
327. Zhang H. Service Disciplines for Guaranteed Performance Service in Packet-Switching Networks. Proceedings of the IEEE October 1995, 1374-1396. No. 10.
328. Zhang H., Ferrari D. Rate-Controlled Static-Priority Queueing. Proceedings of the Annual Joint Conference of the IEEE Computer and Communications Societies (INFOCOM) 1993, 227-236.
329. Cyr G., Bois G., Aboulhamid M. Generation of Processor Interface for SoC Using Standard Communication Protocol. IEE Proceedings of the Computers and Digital Techniques 2004, 367-376. No. 5, Vol.151.
330. http://www.vsi.org.
331. Allen M.S., Lewchuk W.K., Coddington J.D. A High Performance Bus and Cache Controller for PowerPC Multiprocessing Systems. IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD) 1995, 204-211.
332. Hofmann R., Drerup B. Next Generation CoreConnect Processor Local Bus Architecture. IEEE International ASIC/SOC Conference 2002, 221-225.
333. Hardware and Software Platforms: Embedded to Super-computing June 1999, 1-28. Issue 121 Inside the New Computer Industry. A. Allison (Ed.).
334. ARM7DMI Data Sheet 1994, Advanced RISC Machines Ltd, Linkoping, Sweden.
335. Gaisler J. A Portable and Fault-Tolerant Microprocessor Based on the SPARC v8 Architecture. International Conference on Dependable Systems and Networks June 2002, 409-415.
336. Ackland B., et al. A Single-Chip, 1.6-Billion, 16-b MAC/s Multiprocessor DSP. IEEE Journal off Solid-State Circuits March 2000, Vol. 35(No. 3):412-424.
337. Wodey P., Camarroque G., Baray F., Hersemeule R., Cousin J.P. LOTOS Code Generation for Model Checking of STBus Based SoC: The STBus Inter-connect. First ACM and IEEE International Conference on Formal Methods and Models for Co-Design June 2003, 204-213.
338. Keutzer K., Newton A.R., Rabaey J.M., Sangiovanni-Vincentelli A. System-Level Design: Orthogonalization of Concerns and Platform-Based Design. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems December 2000, Vol. 19(No. 12):1523-1543.
339. The importance of sockets in SoC design White paper from. http://www.ocpip.org/socket/whitepapers/.
340. OCP-IP, emphOpen Core Protocol Specification Version 2.0. http://www.ocpip.org.
341. Bhojwani P., Mahapatra R. Interfacing Cores with On-Chip Packet-Switched Networks. International Conference on VLSI Design January 2003, 382-387.
342. Mullins R., Lee J.G., Moore S. Selecting a Timing Regime for On-Chip Networks. Proceedings of the 17th UK Asynchronous Forum September 2005.
343. Bjerregard T., Mahadevan S., Olsen R.G., Sparso J. An OCP Compliant Network Adapter for GALS-Based SoC Design Using the MANGO Network-on-Chip. International Symposium on System-on-Chip November 2005, 171-174.
344. Bolotin E., Cidon I., Ginosar R., Kolodny A. QNoC: QoS Architecture and Design Process for Network on Chip. The Journal of Systems Architecture, Special Issue on Networks on Chip February 2004, Vol. 50(No. 2-3):105-128.
345. Philips Semiconductors Device Transaction Level (DTL) Protocol Specification July 2002, Version 2.2.
346. Lee S.J., Kim K., Kim H., Cho N., Yoo H.J. Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme. Symposium on VLSI circuits 2005, 104-107.
347. Ogras U., Hu J., Marculescu R. Key Research Problems in NoC Design: A Holistic Perspective. Proceedings of the CODES ISSS September 2005, 69-74.
348. Nilsson E., Millberg M., Oberg J., Jantsch A. Load Distribution with the Proximity Congestion Awareness in a Network on Chip. Proceedings of the Design Automation and Test in Europe Conference 2003 2003, 1126-1127.
349. Radulescu A., Dielissen J., Pestana S.G., Gangwal O.P., Rijpkema E., Wielage P., Goossens K. An Efficient On-Chip NI Offering Guaranteed Services, Shared-Memory Abstraction, and Flexible Network Configuration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems January 2005, Vol. 24(No. 1):4-17.
350. Wiklund D., Liu D. Socbus: Switched Network on Chip for Hard Real Time Systems. International Parallel, and Distributed Processing Symposium April 2003.
351. Wolkotte P.T., Smit G.J.M., Rauwerda G.K., Smit L.T. An Energy-Efficient Reconfigurable Circuit-Switched Network-on-Chip. IEEE International Parallel and Distributed Processing Symposium April 2005, 155a.
352. Steenhof F., Duque H., Nilsson B., Goossens K., Llopis P. Networks on Chips for High-End Consumer-Electronics TV System Architectures. Design Automation and Test in Europe Conference March 2006.
353. Angiolini F., Meloni P., Carta S., Benini L., Raffo L. Constrasting a NoC and a Traditional Interconnect Fabric with Layout Awareness. Design Automation and Test in Europe Conference March 2006, 124-129.
354. InterconnectCentric Design for Advanced SoC and NoC April 2004, Kluwer Academic Publisher. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch (Eds.).
355. Scherrer A., Risset T., Fraboulet A. Hardware Wrapper Classification and Requirements for On-Chip Interconnects. Signaux, Circuits et Systmes 2004 2004, 31-34. Monastir, Tunisie.
356. Martin P. Design of a Virtual Component Neutral Network-on-Chip Transaction Layer. Design Automation and Test in Europe Conference 2005, 336-337.
357. Nilsson E., Oeberg J. Reducing power and Latency in 2-D Mesh NoCs Using Globally Pseudochronous Locally Synchronous Clocking. CODES ISSS September 2004, 176-181.
358. Lee S.J., Lee K., Yoo H.J. Analysis and Implementation of Practical, Cost-Effective Networks on Chips. IEEE Design and Test of Computers September-October 2005, 422-433.
359. Svensson E., Seger O., Liu D., Wiklund D., Sathe S. Socbus: The Solution of High Communication Bandwidth On Chip and Short TTM. Real-Time and Embedded Computing Conference September 2002.
360. Dall'Osso M., Biccari G., Giovannini L., Bertozzi D., Benini L. xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multiprocessor SoCs. International Conference on Computer Design 2003, 536-539.
361. Scheffer L. Methodologies and Tools for Pipelined On-Chip Interconnect. International Conference on Computer Design 2002, 152-157.
362. Carloni L.P., McMillan K.L., Sangiovanni-Vincentelli A.L. Theory of Latency-Insensitive Design. IEEE Transactions on CAD of lCs and Systems September 2001, Vol. 20(no. 9):1059-1076.
363. Rijpkema E., Goossens K., Radulescu A., Dielissen J., van Meerbergen J., Wielage P., Waterlander E. Trade-Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. IEE Proceedings of Computers and Digital Techniques September 2003, 294-302. No. 5, Vol. 150.
364. Angiolini F., Meloni P., Bertozzi D., Benini L., Carta S., Raffo L. Networks on Chips: A Synthesis Perspective. Proceedings of the Parallel Computing (ParCo) Conference September 2005.
365. Benini L., De Michli G. Powering Networks on Chips. ISSS 2001, 33-38.
366. ARM AMBA 3.0 AXI Specification March 2004.
367. ARM AMBA 2.0 AHB Specification May 1999.
368. Tanenbaum A.S. Computer Networks 1996, Prentice Hall, Norwell, MA.
369. Gangwal O.P., Radulescu A., Goossens K., Pestana S.G., Rijpkema E. Building Predictable Systems on Chip: An Analysis of Guaranteed Communication in the Aethereal network on Chip. Dynamic and Robust Streaming In and Between Connected Consumer-Electronics Devices 2005, Springer, Upper Saddle River, NJ. P. van der Stok (Ed.).
370. Millberg M., Nilsson E., Thid R., Kumar S., Jantsch A. The Nostrum Backbone - A Communication Protocol Stack for Networks on Chip. International Conference on VLSI Design 2004, 693-696.
371. Ayala J.L., Lopez-Vallejo M., Bertozzi D., Benini L. State-of-the-art SoC communication architectures. Embedded Systems Handbook 2005, CRC Press, Berlin, Germany. R. Zurawski (Ed.).
372. Stergiou S., Angiolini F., Carta S., Raffo L., Bertozzi D., De Micheli G. xpipes Lite: A Synthesis Oriented Design Library for Networks on Chips. Design Automation and Test in Europe Conference 2005, 1188-1193.
373. Radulescu A., Goossens K. Communication Services for Networks on Chip. SAMOS 2002, 275-299.
374. Halfhill T.R. Tensilicas automation arrives: new design tool creates CPU extensions from C/C++ programs. Microprocessor Report July 12, 2004, http://www.MPRonline.com.
375. Leibson S., Kim J. Configurable Processors: A New Era in Chip Design. IEEE Computer July 2005, Vol. 38(No. 7):51-59.
376. Tohara T. A New Kind of Processor Interface for a System-on-a-Chip Processor with TIE Ports and TIE queues of Xtensa LX. Proceedings of the Innovative Architecture for Future Generation High Performance Processors and Systems (IWIA'05) January 2005, 72-79.
377. Ye T.T., Benini L., De Micheli G. Packetized On-Chip Interconnect Communication Analysis for MPSoC. Design Automation and Test in Europe Conference 2003, 10344-10349.
378. http://www.rsim.cs.uiuc.edu/rsim/.
379. Patterson D.A., Hennessy J. Computer Organization and Design. The Hardware/Software Interface 1998, Morgan Kaufmann Publishers, Florida.
380. Dally W.J., Towles B. Principles and Practices of Interconnection Networks 2004, Morgan Kaufmann, San Francisco, CA.
381. Goossens K., Gangwal O.P., Roever J., Niranjan A.P. Interconnect and Memory Organization in SOCs for Advanced Set-Top Boxes and TV - Evolution, Analysis, and Trends. Interconnect-Centric Design for Advanced SoC and NoC 2004, 399-423. Chapter 15, Kluwer, San Fransisco, CA. J. Nurmi, H. Tenhunen, J. Isoaho, A. Jantsch (Eds.).
382. Murali S., Coenen M., Goossens K., Radulescu A., De Micheli G. Mapping and Configuration Methods for Multi-Use-Case Networks on Chips. Proceedings of the Asia and South Pacific Design Automation Conference (ASP-DAC) 2006.
383. Bekooij M., Moreira O., Poplavko P., Mesman B., Pastrnak M., van Meerbergen J. Predictable Embedded multiprocessor System Design. Proceedings of the International Workshop on Software and Compilers for Embedded Systems (SCOPES) September 2004, Springer, Norwell, MA.
384. Bjerregaard T., Sparso J. A Router Architecture for Connection-Oriented Service Guarantees in the MANGO Clockless Network-on-Chip. Proceedings of Design, Automation and Testing in Europe Conference 2005 (DATE05) 2005.
385. Ginosar R. Fourteen Ways to Fool Your Synchronizer. Proceedings of the Ninth International Symposium on Asynchronous Circuits and Systems (ASYNC03) 2003.
386. Posner M., Mossor D. Designing Using the AMBA 3 AXI Protocol. Easing the Design Challenges and Putting the Verification Task on a Fast Track to Success April 2005, Synopsys.
387. Martini F. Design of a Low Latency Circuit Switched NoC Architecture for High Performance MPSoCs. Master thesis March 2006, University of Ferrara.
388. Boekhorst F. Ambient Intelligence, the Next Paradigm for Consumer Electronics: How will it Affect Silicon?. International Solid-State Circuits Conference 2002, Vol. 1:28-31.
389. Declerck G. A Look into the Future of Nanoelectronics. IEEE Symposium on VLSI Technology 2005, 6-10.
390. Ambient Intelligence 2005, Springer, Italy. W. Weber, J. Rabaey, E. Aarts (Eds.).
391. Borkar S., et al. Platform 2015: Intel Processor and Platform Evolution forthe Next Decade. INTEL White Paper 2005.
392. Culler D., Singh J. Parallel Computer Architecture: A Hardware/Software Approach 1999, Morgan Kaufmann Publishers, Berlin, Germany.
393. Hennessy L., Patterson D. Computer Architecture - A Quantitative Approach 2003, Morgan Kaufmann Publishers. 3rd edition.
394. Semiconductor Philips Philips Nexperia Platform http://www.semiconductors.philips.com.
395. Rutten M., et al. Eclipse: Heterogeneous Multiprocessor Architecture for Flexible Media Processing. International Conference on Parallel and Distributed Processing 2002, 39-50.
396. ARM Ltd MPCore Multiprocessors Family http://www.arm.com.
397. Ackland B., et al. A Single Chip, 1.6 Billion, 16-b MAC/s Multiprocessor DSP. IEEE Journal of Solid State Circuits 2000, Vol. 35(No. 3):412-424.
398. Strano G., Tiralongo S., Pistritto C. OCP/STBUS Plug-in Methodology. GSPX Conference 2004.
399. Loghi M., Angiolini F., Bertozzi D., Benini L., Zafalon R. Analyzing On-Chip Communication in a MPSoC Environment. Design and Test in Europe Conference (DATE) 2004, 752-757.
400. Poletti F., Marchal P., Atienza D., Benini L., Catthoor F., Mendias J.M. An Integrated Hardware/Software Approach For Run-Time Scratchpad Management. Design Automation Conference 2004, 238-243.
401. Pham D., et al. The Design and Implementation of a First-generation CELLProcessor. IEEE International Solid-State Circuits Conference 2005, 184-592.
402. Hammond L., et al. The Stanford Hydra CMP. IEEE Micro 2000, Vol. 20(No. 2):71-84.
403. Barroso L., et al. Piranha: A Scalable Architecture Based on Single-chip Multiprocessi. International Symposium on Computer Architecture 2000, 282-293.
404. Intel Semiconductor IXP2850 Network Processor http://www.intel.com.
405. STMicroelectronics Nomadik Platform http://www.st.com.
406. Texas Instruments OMAP5910 Platform http://www.ti.com.
407. Banikazemi M., Govindaraju R., Blackmore R., Panda D. MP-LAPI:An Efficient Implementation of MPI for IBM RS/6000 SP systems. IEEE transactions Parallel and Distributed Systems 2001, Vol. 12(No. 10):1081-1093.
408. Lee W., Dally W., Keckler S., Carter N., Chang A. An Efficient Protected Message Interface. IEEE Computer 1998, Vol. 31(No. 11):68-75.
409. Ramachandran U., Solomon M., Vernon M. Hardware Support for Interprocess Communication. IEEE transactions Parallel and Distributed Systems 1990, Vol. 1(No. 3):318-329.
410. Arakida H., et al. A 160 mW, 80 nA Standby, MPEG-4 Audiovisual LSI 16Mb Embedded DRAM and a 5 GOPS Adaptive Post Filter. IEEE International Solid-State Circuits Conference 2003, 62-63.
411. Gilbert F., Thul M., When N. Communication Centric Architectures for Turbo-decoding on Embedded Multiprocessors. Design and Test in Europe Conference 2003, 351-356.
412. Hand S., Baghdadi A., Bonacio M., Chae S., Jerraya A. An Efficient Scalable and Flexible Data Transfer Architectures for Multiprocessor SoC with Massive Distributed Memory. Design Automation Conference 2004, 250-255.
413. Paulin P., Pilkington C., Bensoudane E. StepNP: A system-level Exploration Platform for Network Processors. IEEE Design and Test of Computers 2002, Vol.19(No. 6):17-26.
414. Stenstrom P. A Survey of Cache Coherence Schemes for Multiprocessors. IEEE Computer 1990, Vol. 23(No. 6):12-24.
415. Tomasevic M., Milutinovic V.M. Hardware Approaches to Cache Coherence in Shared-Memory Multiprocessors. IEEE Micro 1994, Vol. 14(No. 5-6):52-59.
416. Tartalja I., Milutinovic V.M. Classifying Software-Based Cache Coherence Solutions. IEEE Software 1997, Vol. 14(No. 3):90-101.
417. Kongetira P., Aingaran K., Olukotun K. Niagara: a 32-way Multithreaded Sparc Processor. IEEE Micro 2005, Vol. 25(No. 2):21-29.
418. Sutter H., Larus J. Software and the Concurrency Revolution. ACM Queue 2005, Vol. 3(No. 7):54-62.
419. Stephens R. A Survey of Stream Processing. Acta Informatica 1997, Vol. 34(No. 7):491-541.
420. Lee E., Messerschmitt D. Pipeline Interleaved Programmable DSPs: Synchronous Data Flow Programming. IEEE Transactions on Signal Processing 1987, Vol. 35(No. 9):1334-1345.
421. Thies W., et al. Language and Compiler Design for Streaming Applications. IEEE International Parallel and Distributed Processing Symposium 2004, 201.
422. Hive Silicon AVISPA-CH. http://www.siliconhive.com.
423. Bekoij M. Constraint Driven Operation Assignment for Retargetable VLIW Compilers. Ph.D. Dissertation 2004.
424. Allen R., Kennedy K. Optimizing Compilers for Modern Architectures: A Dependence-based Approach 2001, Morgan-Kaufman.
425. Faraboschi P., Fisher J., Young C. Instruction Scheduling for Instruction Level Parallel Processors. Proceedings of the IEEE 2001, 1638-1659. vol. 89, No. 11.
426. Taylor M., Lee W., Amarasinghe S., Agarwal A. Scalar Operand Networks. IEEE Transactions on Parallel and Distributed Systems 2005, Vol. 16(No.2):145-162.
427. Mattson P., et al. Communication Scheduling. ACM Conference on Architectural Support for Programming Languages and Operating Systems 2000, 82-92.
428. Sato M. OpenMP: Parallel Programming API for Shared Memory Multiprocessors and On-chip Multiprocessors. IEEE International Symposium on System Synthesis 2002, 109-111.
429. Genko N., Atienza D., De Micheli G., Mendias J., Hermida R., Catthoor F. A Complete Network-on-chip Emulation Framework. Design, Automation and Test in Europe 2005, Vol. 1:246-251.
430. Shin C., et al. Fast Exploration of Parameterized Bus Architecture for Communication-centric SoC Design. Design, Automation and Test in Europe 2004, Vol. 1:352-357.
431. Michael M. Scalable, Lock-free Dynamic memory Allocation. ACM Conference on Programming Languages Design and Implementation 2004, 110-122.
432. Ahonen T., Siguenza-Tortosa D.A., Bin H., Nurmi J. Topology Optimization for Application Specific Networks on Chip. SLIP, International Workshop on System Level Interconnect Prediction February 2004, 53-60.
433. Benini L., Bertozzi D., Bogliolo A., Menichelli F., Olivieri M. MPARM:Exploring the Multi-processor SoC Design Space with SystemC. Journal of VLSI Signal Processing 2005, Vol. 41:169-182.
434. Bertozzi D., Jalabert A., Murali S., Tamhankar R., Stergiou S., Benini L., De Micheli G. NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip. IEEE Transactions on Parallel and Distributed Systems February 2005, Vol. 16(No. 2):113-129.
435. Dall'Osso M., Biccari G., Giovannini L., Bertozzi D., Benini L. xpipes: A Latency Insensitive Parameterized Network-on-Chip Architecture for Multi-processor SoCs. International Conference on Computer Design 2003, 536-539.
436. Dielissen J., Radulescu A., Goossens K. Power measurements and analysis of a network on chip 2005, Technical Note 2005/00282, Philips Research.
437. Gangwal O.P., Rǎdulescu A., Goossens K., Pestana S.González, Rijpkema E. Building Predictable Systems on Chip: An Analysis of Guar-anteed Communication in the Æthereal Network on Chip. Philips Research Book Series 2005, 1-36. Chapter 1, Springer. P. van der Stok (Ed.).
438. Genko N., Atienza D., Mendias J., Hermida R., De Micheli G., Catthoor F. A Complete Network-on-Chip Emulation Framework. DATE, International Conference on Design and Test Europe 2005, 246-251.
439. Goossens K., Dielissen J., Gangwal O.P., Pestana S.Gonzalez, Rǎdulescu A., Rijpkema E. A Design Flow for Application-Specific Networks on Chip with Guaranteed Performance to Accelerate SoC Design and Verification. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2005, 1182-1187.
440. Hansson A., Goossens K., Rǎdulescu A. A Unified Approach to Con-strained Mapping and Routing on Network-on-Chip Architectures. International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS) September 2005.
441. Ho W.H., Pinkston T.M. A Methodology for Designing Efficient On-Chip Interconnects on Weil-Behaved Communication Patterns. HPCA, International Symposium on High-Performance Computer Architecture February 2003, 377-388.
442. Hu J., Marculescu R. Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures. DATE, International Conference on Design and Test Europe March 2003, 10688-10693.
443. Jalabert A., Murali S., Benini L., De Micheli G. xpipesCom-piler: A Tool for Instantiating Application Specific Networks on Chip. DATE, International Conference on Design and Test Europe February 2004, 884-889.
444. Kumar S., Jantsch A., Soininen J., Forsell M., Millberg M., Oberg J., Tiensyrj K., Hemani A. A Network on Chip Architecture and Design Methodology. Proceedings of the IEEE Computer Society Annual Symposium on VLSI 2002, 105-112.
445. Lee S.-Y., Song S.-J., Lee K., Woo J.-H., Kim S.-E., Nam B.-G., Yoo H.-J. An 800 MHz Star-Connected On-Chip Network for Application to Systems on a Chip. IEEE Solid-State Circuits Conference 2003, 468-469.
446. Lee S.-Y., Lee K., Song S.-J., Yoo H.J. Packet-Switched On-Chip Interconnection Network for System-on-Chip Applications. IEEE Transactions on Circuits and Systems, Part II: Express Briefs June 2005, Vol. 52(No. 6):308-312.
447. Marescaux T., Mignolet J., Bartic A., Moffat W., Verkest D., Vernalde S., Lauwereins R. NoC As a Hw Component of an OS for Reconfigurable Systems. FPL, Field Programmable Logic, 2003 June 2004, 595-605.
448. Murali S., De Micheli G. SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs. DAC, Design Automation Conference June 2004, 914-919.
449. Murali S., Meloni P., Angiolini F., Atienza D., Carta S., Benini L., De Micheli G., Raffo L. Designing Message Dependent Deadlock Free Networks on Chips for Application Specific Systems on Chips. Proceedings of the VLSI-SoC 2006.
450. Murali S., Benini L., De Micheli G. Mapping and Physical Planning of Networks on Chip Architectures with Quality-of-Service Guarantees. ASPDAC, Asia South Pacific Design Automation Conference January 2005, 27-32.
451. Murali S., Coenen M., Rǎdulescu A., Goossens K., De Micheli G. A Methodology for Mapping Multiple Use-Cases on to Networks on Chip. DATE, International Conference on Design and Test Europe March 2006.
452. Pinto A., Carloni L., Sangiovanni-Vincentelli A. Efficient Synthesis of Networks on Chip. ICCD, International Conference on Computer Design October 2003, 146-150.
453. Radulescu A., Dielissen J., Pestana S.González, Gangwal O.P., Rijpkema E., Wielage P., Goossens K. An Efficient On-Chip Network Interface Offering Guaranteed Services, Shared-Memory Abstraction, and flexible Network Programming. IEEE Transactions on CAD of Integrated Circuits and Systems January 2005, Vol. 21(No. 1):4-17.
454. Rijpkema E., Goossens K.G.W., Radulescu A., Dielissen J., van Meerbergen J., Wielage P., Waterlander E. Trade Offs in the Design of a Router with Both Guaranteed and Best-Effort Services for Networks on Chip. Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE) March 2003, 350-355.
455. Siguenza-Tortosa D., Nurmi J. Proteo: A New Approach to Network on Chip. CSN, Conference on Communication Systems and Network 2002.
456. Stergios S., Angiolini F., Bertozzi D., Carta S., Raffo L., De Micheli G. xpipesLite: A Synthesis-Oriented Design Flow for Networks on Chip. DATE, International Conference on Design and Test Europe 2002, 1188-1193.
457. Weber W., et al. A Quality-of-Service Mechanism for Interconnection Networks is System-on-Chips. Proceedings of the Design, Automation and Test in Europe Conference 2005, 1232-1237.
458. http://www.arm.com/products/solutions/AMBAOverview.html.
459. http://www.st.com/stonline/prodpres/dedicate/soc/cores/stbus.htm.
460. http://www.isi.edu/nsnam/ns/.
461. http://www.swarm.org.
462. http://www.ocpip.org.
463. http://www.sonicsinc.com.
464. http://www.vsi.org.
465. http://www.synopsys.com/products/verification/verification.html.
466. http://www.cadence.com/verisity/.
467. http://www.coware.com/.
468. http://www.synopsys.com/products/designware/core_assembler.html.
469. http://www.arteris.com.
470. Borgatti M., et al. A Multi-Context 6.4 Gb/s/Channel On-Chip Communication Network Using 0.18 μm Flash-EEPROM Switches and Elastic Interconnects. IEEE International Solid-State Circuits Conference February 2003, 466-467.
471. Chung D., et al. A Chip-Package Hybrid DLL Loop and Clock Distribution Network for Low-Jitter Clock Delivery. IEEE International Solid-State Circuits Conference February 2005, 514-515.
472. Lee K., et al. A 51 mW 1.6 GHz On-Chip Network for Low-Power Heterogeneous SoC Platform. IEEE International Solid-State Circuits Conference February 2004, 152-153.
473. Lee K., et al. SILENT: Serialized Low-Energy Transmission Coding for On-Chip Interconnection Networks. IEEE International Conference on Computer Aided Design November 2004, 448-451.
474. Lee K., et al. An Exploration of Hierarchical Topologies for Networks-on-Chip. Design, Automation and Test in Europe Conference 2006, submitted to.
475. Lee S.-J., et al. An 800 MHz Star-Connected On-Chip Network for Application to Systems on a Chip. IEEE International Solid-State Circuits Conference February 2003, 468-469.
476. Lee S.-J. Cost-Optimized System-on-Chip Implementation with On-Chlip Network. Ph.D. thesis 2005, Korea Advanced Institute of Science and Technology, Berlin, Germany.
477. Lee S.-J., et al. Adaptive Network-on-Chip with Wave-Front Train Serialization Scheme. Digest Technical Papers June 2005, 104-107.
478. Sohn J.-H., et al. A 50 Mvertices/s Graphics Processor with Fixed-Point Programmable Vertex Shader for Mobile Applications. IEEE International Solid-State Circuits Conference February 2005, 192-193.
479. Talyor M.B., et al. A 16-Issue Multiple-Program-Counter Microprocessor with Point-to-Point Scalar Operand Network. IEEE International Solid-State Circuits Conference February 2003, 170-171.
480. Taylor M., Lee W., Amarasinghe S., Agrawal A. Scalar Operand Networks. IEEE Transactions on Parallel and Distributed Systems February 2005, Vol. 16(No. 2):1-18.
481. Zhang H., et al. A 1V Heterogeneous Reconfigurable Processor IC for Baseband Wireless Applications. IEEE International Solid-State Circuits Conference February 2000, 68-69.
482. Zhang H., et al. Low-Swing On-Chip Signaling Techniques: Effectiveness and Robustness. IEEE Transactions on VLSI systems June 2000, Vol. 8:264-272.