메뉴 건너뛰기




Volumn II, Issue , 2005, Pages 1176-1181

An application-specific design methodology for STbus crossbar generation

Author keywords

Application specific; Bus; Crossbar; Networks on Chips; SystemC; Systems on Chips

Indexed keywords

COMMUNICATION ARCHITECTURES; MULTIPROCESSOR SYSTEMS ON CHIPS (MPSOC); STANDARD BUS PRODUCTS;

EID: 33646944677     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2005.50     Document Type: Conference Paper
Times cited : (56)

References (23)
  • 1
    • 0036047772 scopus 로고    scopus 로고
    • Component-based design approach for multi-core SoCs
    • June
    • W.Cesario et al., "Component-Based Design Approach for Multi-Core SoCs", DAC 2002, pp.789-794, June, 2002.
    • (2002) DAC 2002 , pp. 789-794
    • Cesario, W.1
  • 2
    • 0036149420 scopus 로고    scopus 로고
    • Networks on chips: A new SoC paradigm
    • Jan.
    • L.Benini, G.D.Micheli, "Networks on Chips: A New SoC Paradigm", IEEE Computers, pp. 70-78, Jan. 2002.
    • (2002) IEEE Computers , pp. 70-78
    • Benini, L.1    Micheli, G.D.2
  • 4
    • 84955516546 scopus 로고    scopus 로고
    • A methodology for designing efficient on-chip interconnects on well-behaved communication patterns
    • Feb
    • W.H.Ho, T.M.Pinkston, "A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns", HPCA 2003, pp. 377-388, Feb 2003.
    • (2003) HPCA 2003 , pp. 377-388
    • Ho, W.H.1    Pinkston, T.M.2
  • 5
    • 0029547607 scopus 로고
    • Communication synthesis for distributed embedded systems
    • Nov.
    • T. Yen, W. Wolf, "Communication synthesis for distributed embedded systems", Proc. ICCAD, pp.288-294, Nov. 1995.
    • (1995) Proc. ICCAD , pp. 288-294
    • Yen, T.1    Wolf, W.2
  • 6
    • 0029505681 scopus 로고
    • Synthesis of system-level communication by an allocation based approach
    • Sept.
    • J. Daveau et al., "Synthesis of system-level communication by an allocation based approach", Proc. ISSS, pp. 150-155, Sept. 1995.
    • (1995) Proc. ISSS , pp. 150-155
    • Daveau, J.1
  • 7
    • 0005419196 scopus 로고    scopus 로고
    • Bus-based communication synthesis on system level
    • ACM TODAES
    • M. Gasteier, M. Glesner, "Bus-based communication synthesis on system level", ACM Trans. Design Automation Electron. Syst., ACM TODAES, vol.4, no.1, pp. 1-11, 1999.
    • (1999) ACM Trans. Design Automation Electron. Syst. , vol.4 , Issue.1 , pp. 1-11
    • Gasteier, M.1    Glesner, M.2
  • 8
    • 14644388576 scopus 로고    scopus 로고
    • Automated bus generation for multiprocessor SoC design
    • March
    • K. Ryu, V. Mooney, "Automated Bus Generation for Multiprocessor SoC Design, Proc. DATE, pp. 282-287, March 2003.
    • (2003) Proc. DATE , pp. 282-287
    • Ryu, K.1    Mooney, V.2
  • 9
    • 2942604532 scopus 로고    scopus 로고
    • Design space exploration for optimizing on-chip communication architectures
    • June
    • K.Lahiri et al., "Design Space Exploration for Optimizing On-Chip Communication Architectures", IEEE TCAD, vol.23, no.6, pp. 952-961, June 2004.
    • (2004) IEEE TCAD , vol.23 , Issue.6 , pp. 952-961
    • Lahiri, K.1
  • 10
    • 2542430318 scopus 로고    scopus 로고
    • Design of high-performance system-on-chips using communication architecture tuners
    • May
    • K.Lahiri et al., "Design of High-Performance System-on-Chips using Communication Architecture Tuners", IEEE TCAD, vol.23, no.5, pp. 620-636, May 2004.
    • (2004) IEEE TCAD , vol.23 , Issue.5 , pp. 620-636
    • Lahiri, K.1
  • 11
    • 84893753441 scopus 로고    scopus 로고
    • Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip
    • Mar
    • E.Rijpkema et al., "Trade-offs in the design of a router with both guaranteed and best-effort services for networks on chip", DATE 2003, pp. 350-355, Mar 2003.
    • (2003) DATE 2003 , pp. 350-355
    • Rijpkema, E.1
  • 12
    • 84893687806 scopus 로고    scopus 로고
    • A generic architecture for on-chip packet switched interconnections
    • March
    • P.Guerrier, A.Greiner,"A generic architecture for on-chip packet switched interconnections", Proc. DATE, pp. 250-256, March 2000.
    • (2000) Proc. DATE , pp. 250-256
    • Guerrier, P.1    Greiner, A.2
  • 13
    • 0037656855 scopus 로고    scopus 로고
    • A network on chip architecture and design methodology
    • S.Kumar et al., "A network on chip architecture and design methodology," ISVLSI 2002, pp. 105-112, 2002.
    • (2002) ISVLSI 2002 , pp. 105-112
    • Kumar, S.1
  • 14
    • 3042567207 scopus 로고    scopus 로고
    • Bandwidth constrained mapping of cores onto NoC architectures
    • S.Murali, G.De Micheli, Bandwidth Constrained Mapping of Cores onto NoC Architectures, vol. 2, pp. 20896-20902, Proc. DATE 2004.
    • Proc. DATE 2004 , vol.2 , pp. 20896-20902
    • Murali, S.1    De Micheli, G.2
  • 15
    • 4444335188 scopus 로고    scopus 로고
    • SUNMAP: A tool for automatic topology selection and generation for NoCs
    • S.Murali, G.DeMicheli, SUNMAP: A Tool for Automatic Topology Selection and Generation for NoCs, pp.914-919, DAC 2004.
    • DAC 2004 , pp. 914-919
    • Murali, S.1    Demicheli, G.2
  • 17
    • 3042669096 scopus 로고    scopus 로고
    • QNoC: QoS architecture and design process for network on chip
    • Dec
    • E. Bolotin. et al., "QNoC: QoS architecture and design process for Network on Chip", The Journal of Systems Architecture, Dec 2003.
    • (2003) The Journal of Systems Architecture
    • Bolotin, E.1
  • 18
    • 0036045512 scopus 로고    scopus 로고
    • Constraint-driven communication synthesis
    • June
    • A. Pinto et. al. "Constraint-Driven Communication Synthesis", Proc. DAC 02, p. 783-788, June 2002.
    • (2002) Proc. DAC 02 , pp. 783-788
    • Pinto, A.1
  • 19
    • 0344119476 scopus 로고    scopus 로고
    • Efficient synthesis of networks on chip
    • Oct
    • A.Pinto et. al, "Efficient Synthesis of Networks on Chip", ICCD 2003, pp. 146-150, Oct 2003.
    • (2003) ICCD 2003 , pp. 146-150
    • Pinto, A.1
  • 20
    • 84954421164 scopus 로고    scopus 로고
    • Energy-aware mapping for tile-based NOC architectures under performance constraints
    • J.Hu, R.Marculescu,"Energy-Aware Mapping for Tile-based NOC Architectures Under Performance Constraints", ASP-DAC 2003.
    • ASP-DAC 2003
    • Hu, J.1    Marculescu, R.2
  • 21
    • 84893760422 scopus 로고    scopus 로고
    • Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures
    • March
    • J.Hu, R.Marculescu, "Exploiting the Routing Flexibility for Energy/Performance Aware Mapping of Regular NoC Architectures", Proc. DATE 2003, March 2003.
    • (2003) Proc. DATE 2003
    • Hu, J.1    Marculescu, R.2
  • 22
    • 4444300275 scopus 로고    scopus 로고
    • Analyzing on-chip communication in a MPSoC environment
    • Feb
    • M. Loghi et al., "Analyzing On-Chip Communication in a MPSoC Environment", Proc. DATE 2004, pp. 20752-20757, Feb 2004.
    • (2004) Proc. DATE 2004 , pp. 20752-20757
    • Loghi, M.1
  • 23
    • 84858947806 scopus 로고    scopus 로고
    • ILOG CPLEX, "http://www.ilog.com/products/cplex/"


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.