Toward achieving energy efficiency in presence of deep submicron noise

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 8, Issue 4, 2000, Pages 379-391

  Hegde, Rajamohana ^a,b   Shanbhag, Naresh R ^a,b  

^a IEEE   (United States)

^b University of Illinois at Urbana Champaign   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DEEP SUBMICRON NOISE; NOISE-TOLERANT COMPUTING;

ELECTRIC NETWORK ANALYSIS; ELECTRIC NETWORK SYNTHESIS; ENERGY DISSIPATION; ENERGY EFFICIENCY; ENERGY UTILIZATION; INTEGRATED CIRCUIT LAYOUT; SIGNAL ENCODING; SPURIOUS SIGNAL NOISE;

VLSI CIRCUITS;

EID: 0034245046     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/92.863617     Document Type: Article

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