Low power error resilient encoding for on-chip data buses

Proceedings -Design, Automation and Test in Europe, DATE

Volumn , Issue , 2002, Pages 102-109

  Bertozzi, Davide ^a   Benini, Luca ^a   De Micheli, Giovanni ^b  

^a UNIVERSITY OF BOLOGNA   (Italy)

^b STANFORD UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

DECODING COMPLEXITY; DECODING OVERHEADS; DETECTION CAPABILITY; ENERGY EFFICIENT; ON-CHIP INTERCONNECTS; POWER-SUPPLY NOISE; RADIATION-INDUCED EFFECTS; RETRANSMISSION STRATEGIES;

COMPUTER ARCHITECTURE; DATA TRANSFER; ENERGY EFFICIENCY; ERROR CORRECTION; EXHIBITIONS;

DECODING;

EID: 84893755546     PISSN: 15301591     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DATE.2002.998256     Document Type: Conference Paper

References (18)

1. K. Aingaran, F. Klass, C. M. Kim, C. Amir, J. Mitra, E. You, J. Mohd, and S. K. Dong. "Coupling Noise Analysis for VLSI and ULSI Circuits". IEEE ISQED 2000, pages 485-489, March 2000.
2. L. Anghel and M. Nicolaidis. "Cost Reduction and Evaluation of Temporary Faults Detecting Technique". DATE 2000, pages 591-598, March 2000.
3. L. Anghel and M. Nicolaidis. "Evaluation of Temporary Fault Tolerant IC Architectures to the Rescue of Nanometer Technologies". MEDEA A-401 2nd Public Workshop, 2000.
4. J. A. Davis et al. "Interconnect Limits on Gigascale Integration (GSI) in the 21st Century". Proceedings of the IEEE, 89(3):305-324, March 2001.
5. R. Hegde and N. R. Shanbhag. "Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise". IEEE Trans. on VLSI Systems, 8(4):379-391, August 2000.
6. R. Ho, K. W. Mai, and M. A. Horowitz. "The Future of Wires". Proc. of the IEEE, 89(4):490-504, April 2001.
7. A. Krstic, Y. M. Jiang, and K. T. Cheng. "Pattern Generation for Delay Testing and Dynamic Timing Analysis Considering Power-Supply Noise Effects". IEEE Transactions on CAD, 20(3):416-425, March 2001.
8. S. Lin and D. J. Costello. Error Control Coding: Fundamentals and Applications. Prentice-Hall, Engl. Cliffs, 1983.
9. D. Liu et al. "Power Consumption Estimation in CMOS VLSI Chips". IEEE Journal of Solid-State Circuits, 29:663-670, June 1994.
10. C. Metra and M. Favalli. "Bus Crosstalk Fault-Detection Capabilities of Error-Detecting Codes for On-Line Testing". IEEE Trans. on VLSI Systems, 7(3):392-396, Sept. 1999.
11. C. Metra and B. Ricco. "Optimization of Error Detecting Codes for the Detection of Crosstalk Originated Errors". DATE 2001, pages 290-296, March 2001.
12. R. L. Pickholtz. Digital Systems Testing and Testable Design. Computer Science Press, New York, 1990.
13. K. L. Shepard and V. Narayanan. "Noise in Deep Submicron Digital Design". IEEE/ACM ICCAD-96, pages 524-531, November 1996.
14. C. Svensson. "Optimum Voltage Swing on On-Chip and Off-Chip Interconnect". IEEE Journal of Solid-State Circuits, 36(7):1108-1112, July 2001.
15. J. F. Wakerly. Digital Design: Principles and Practices. Prentice-Hall, Upper Saddle River, Third Edition 2000.
16. http://www.gaisler.com. Gaisler Research Website.
17. H. Zhang, V. George, and J. M. Rabaey. "Low Swing On-Chip Signaling Techniques: Effectiveness and Robustness". IEEE Trans. on VLSI Systems, 8(3):264-272, June 2000.
18. M. Zorzi. "Some Results on Error Control for Burst-Error Channels under Delay Constraints". IEEE Trans. on Vehicular Technology, 50(1):12-24, January 2001.