The design and implementation of a first-generation CELL processor

Digest of Technical Papers - IEEE International Solid-State Circuits Conference

Volumn 48, Issue , 2005, Pages

  Pham, D ^a   Asano, S ^c   Bolliger, M ^a   Day, M N ^a   Hofstee, H P ^a   Johns, C ^a   Kahle, J ^a   Kameyama, A ^c   Keaty, J ^a   Masubuchi, Y ^a   Riley, M ^a   Shippy, D ^a   Stasiak, D ^a   Suzuoki, M ^b   Wang, M ^a   Warnock, J ^a   Weitzel, S ^a   Wendel, D ^a   Yamazaki, T ^b   Yazawa, K ^b  

^a IBM   (United States)

^b SONY CORPORATION   (Japan)

^c TOSHIBA CORPORATION   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 27344435504     PISSN: 01936530     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (2)

1. B. Flachs et al., "A Streaming Processor Unit for a CELL Processor," ISSCC Dig. Tech. Papers, Paper 7.4, pp. 134-135, Feb., 2005.
2. T. Asano et al., "A 4.8GHz Fully Pipelined Embedded SRAM in the Streaming Processor of a CELL Processor," ISSCC Dig. Tech. Papers, Paper 26.7, pp. 486-487, Feb., 2005.