LOTOS code generation for model checking of STBus based SoC: The STBus interconnection

Proceedings - 1st ACM and IEEE International Conference on Formal Methods and Models for Co-Design, MEMOCODE 2003

Volumn , Issue , 2003, Pages 204-213

  Wodey, P ^a   Camarroque, G ^a   Baray, F ^a   Hersemeule, R ^b   Cousin, J P ^b  

^a UNIVERSITÉ BLAISE PASCAL   (France)

^b Advanced System Technology Lab   (France)

Author keywords

Collaborative work; Communication channels; Computer architecture; Laboratories; Logic; Microelectronics; Process design; System buses; System recovery; System on a chip

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; AUTOMATIC PROGRAMMING; BUSES; CODES (SYMBOLS); COMMUNICATION CHANNELS (INFORMATION THEORY); COMPUTER ARCHITECTURE; COMPUTER SYSTEM RECOVERY; DESIGN; DISTRIBUTED COMPUTER SYSTEMS; FORMAL METHODS; INTEGRATED CIRCUIT INTERCONNECTS; LABORATORIES; MICROELECTRONICS; MICROPROCESSOR CHIPS; MODEL CHECKING; NETWORK COMPONENTS; PROCESS DESIGN; PROGRAM COMPILERS; PROGRAMMABLE LOGIC CONTROLLERS; SYSTEM BUSES;

COLLABORATIVE WORK; INDUSTRIAL COMPANIES; LABELED TRANSITION SYSTEMS; LOGIC; SOC (SYSTEM ON CHIP); SYSTEM ON A CHIP; SYSTEM RECOVERY; TEMPORAL LOGIC FORMULA;

SYSTEM-ON-CHIP;

EID: 34548346286     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MEMCOD.2003.1210105     Document Type: Conference Paper

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