Optimum voltage swing on on-chip and off-chip interconnect

IEEE Journal of Solid-State Circuits

Volumn 36, Issue 7, 2001, Pages 1108-1112

  Svensson, Christer ^a,b  

^a IEEE   (Sweden)

^b LINKÖPING UNIVERSITY   (Sweden)

Author keywords

Integrated circuits; Interconnections; Power consumption; Voltage swing

Indexed keywords

POWER CONSUMPTION; VOLTAGE SWING;

AMPLIFIERS (ELECTRONIC); ELECTRIC POTENTIAL; GAIN MEASUREMENT; INTEGRATED CIRCUIT MANUFACTURE; INTERCONNECTION NETWORKS; LEAKAGE CURRENTS; SEMICONDUCTOR DEVICE MODELS; TRANSCONDUCTANCE;

CMOS INTEGRATED CIRCUITS;

EID: 0035392122     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.933468     Document Type: Article

References (8)

1. Power consumption estimation in CMOS VLSI chips
2. A comparison of dissipated-power and signal-to-noise ratios in electrical and optical interconnects
3. Optimum voltage swing on on-chip and off-chip interconnects
4. A high-performance 180-nm generation logic technology
5. Sub-1-V swing internal bus architecture for future low-Power ULSIs
6. I/O family with 200 m V to 500 m V supply voltage
7. Low power circuit techniques