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Volumn , Issue , 2002, Pages 195-202

Managing power and performance for system-on-chip designs using voltage islands

Author keywords

[No Author keywords available]

Indexed keywords

POWER CONSUMPTION; POWER DENSITY; SYSTEM-ON-CHIP DESIGNS; VOLTAGE ISLANDS;

EID: 0036911921     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774601     Document Type: Conference Paper
Times cited : (262)

References (13)
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    • Enomoto, E., "Low Power Design Technology for Digital LSIs," IEICE Transactions on Electronics v E79-C n 12, Dec. 1996, pp 1639-1649.
    • (1996) IEICE Transactions on Electronics , vol.E79-C , Issue.12 , pp. 1639-1649
    • Enomoto, E.1
  • 3
    • 0032592096 scopus 로고    scopus 로고
    • Design challenges of technology scaling
    • July-August
    • Borkar, S., "Design Challenges of Technology Scaling," IEEE Micro, Vol. 19, No. 4, July-August 1999, p 23-29.
    • (1999) IEEE Micro , vol.19 , Issue.4 , pp. 23-29
    • Borkar, S.1
  • 4
    • 0035445422 scopus 로고    scopus 로고
    • OFF-state leakage current mechanisms in bulkSi and SOI MOSFETs and their impact on CMOS ULSIs standby current
    • Sept.
    • Adan, A.O. and Higashi K., "OFF-State Leakage Current Mechanisms in BulkSi and SOI MOSFETs and Their Impact on CMOS ULSIs Standby Current," IEEE Transactions on Electron Devices, Vol. 48, No. 9, Sept. 2001, pp 2050-2057.
    • (2001) IEEE Transactions on Electron Devices , vol.48 , Issue.9 , pp. 2050-2057
    • Adan, A.O.1    Higashi, K.2
  • 6
    • 0036507826 scopus 로고    scopus 로고
    • Maintaining the benefits of CMOS scaling when scaling bogs down
    • March/May
    • Nowack, E.J., "Maintaining the Benefits of CMOS Scaling when Scaling Bogs Down," IBM Journal of Research and Development, No. 2/3 March/May 2002.
    • (2002) IBM Journal of Research and Development , Issue.2-3
    • Nowack, E.J.1
  • 7
    • 0012109564 scopus 로고    scopus 로고
    • Low power microprocessor design
    • Kluwer Academic Publishers
    • Gary, S., "Low Power Microprocessor Design," Low Power Design Methodologies, Kluwer Academic Publishers, 1996, pp 279-281.
    • (1996) Low Power Design Methodologies , pp. 279-281
    • Gary, S.1
  • 8
    • 0004311631 scopus 로고    scopus 로고
    • IC Wizard - The hierarchical design planning tool
    • © 2002 Monterey Design Systems, Inc.
    • "IC Wizard - The Hierarchical Design Planning Tool," © 2002 Monterey Design Systems, Inc., http://www.mondes.com/prod_icw.html
  • 9
    • 0004315164 scopus 로고    scopus 로고
    • TeraForm® RTL design planner for deep submicron SOCs
    • © 2002 Tera Systems, Inc.
    • "TeraForm® RTL Design Planner for Deep Submicron SOCs," © 2002 Tera Systems, Inc., http://www.terasystems.com/products/datasheet.htm
  • 10
    • 4243247614 scopus 로고    scopus 로고
    • First encounter
    • © 2002 Cadence Design Systems, Inc.
    • "First Encounter," © 2002 Cadence Design Systems, Inc., http://www.cadence.com/products/first_encounter.html
  • 11
    • 0012111305 scopus 로고    scopus 로고
    • 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System, copyright 1999 by IEEE
    • 1481-1999 IEEE Standard for Integrated Circuit (IC) Delay and Power Calculation System, copyright 1999 by IEEE.


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.