Power-driven design of router microarchitectures in on-chip networks

Proceedings of the Annual International Symposium on Microarchitecture, MICRO

Volumn 2003-January, Issue , 2003, Pages 105-116

  Wang, Hangsheng ^a   Peh, Li Shiuan ^a   Malik, S ^a  

^a Princeton University   (United States)

Author keywords

Bandwidth; Fabrics; Intelligent networks; Microarchitecture; Network on a chip; Power dissipation; Power system interconnection; System on a chip; Telecommunication traffic; Traffic control

Indexed keywords

ADAPTIVE SYSTEMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; BANDWIDTH; COMPUTER ARCHITECTURE; ELECTRIC LOSSES; EMBEDDED SYSTEMS; ENERGY DISSIPATION; FABRICS; INTEGRATED CIRCUIT DESIGN; INTELLIGENT NETWORKS; MICROPROCESSOR CHIPS; MULTIPROCESSING SYSTEMS; NETWORK ARCHITECTURE; PROGRAM PROCESSORS; SWITCHING NETWORKS; SYSTEM-ON-CHIP; TELECOMMUNICATION TRAFFIC; TRAFFIC CONTROL;

CHIP MULTIPROCESSOR; INTERCONNECT FABRICS; MICRO ARCHITECTURES; NETWORK ON A CHIP; ON CHIP COMMUNICATION; POWER SYSTEM INTERCONNECTION; SYSTEM ON A CHIP; SYSTEMS-ON-A CHIPS;

INTEGRATED CIRCUIT INTERCONNECTS;

EID: 84862144932     PISSN: 10724451     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/MICRO.2003.1253187     Document Type: Conference Paper

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