A Fault Model Notation and Error-Control Scheme for Switch-to-Switch Buses in a Network-on-Chip

Hardware/Software Codesign - Proceedings of the International Workshop

Volumn , Issue , 2003, Pages 188-193

  Zimmer, Heiko ^a   Jantsch, Axel ^b  

^a DARMSTADT UNIVERSITY OF TECHNOLOGY   (Germany)

^b ROYAL INSTITUTE OF TECHNOLOGY   (Sweden)

Author keywords

Bus Encoding; Fault Tolerance; Network on Chip

Indexed keywords

BUS ENCODING; NETWORK-ON-CHIP;

BANDWIDTH; BINARY CODES; COMPUTER SIMULATION; CROSSTALK; DATA COMMUNICATION SYSTEMS; ELECTRIC SWITCHES; ENCODING (SYMBOLS); ERROR DETECTION; FAULT TOLERANT COMPUTER SYSTEMS; INTERCONNECTION NETWORKS; MATHEMATICAL MODELS; PACKET NETWORKS; PARAMETER ESTIMATION; QUALITY OF SERVICE;

COMPUTER NETWORKS;

EID: 1142287741     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/944691.944694     Document Type: Conference Paper

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