A robust self-calibrating transmission scheme for on-chip networks

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Volumn 13, Issue 1, 2005, Pages 126-139

  Worm, Frédéric ^a   Ienne, Paolo ^a   Thiran, Patrick ^a   De Micheli, Giovanni ^b  

^a EPFL   (Switzerland)

^b Stanford University   (United States)

Author keywords

Electrical parameter variations; Interconnect for networks on chip; Low power systems on chip (SoC); Self calibrating designs; VLSI design methodology

Indexed keywords

CALIBRATION; CMOS INTEGRATED CIRCUITS; CONTROL EQUIPMENT; EMBEDDED SYSTEMS; ENERGY UTILIZATION; ERROR ANALYSIS; GRAPH THEORY; POISSON DISTRIBUTION; SIGNAL INTERFERENCE; VLSI CIRCUITS; VOLTAGE CONTROL;

ELECTRICAL PARAMETER VARIATIONS; INTERCONNECT FOR NETWORKS-ON-CHIP; LOW-POWER SYSTEMS-ON-CHIP (SOC); SELF-CALIBRATING DESIGNS; VLSI DESIGN METHODOLOGY;

MICROPROCESSOR CHIPS;

EID: 13144293111     PISSN: 10638210     EISSN: None     Source Type: Journal    
DOI: 10.1109/TVLSI.2004.834241     Document Type: Article

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