SoCBUS: Switched network on chip for hard real time embedded systems

Proceedings - International Parallel and Distributed Processing Symposium, IPDPS 2003

Volumn , Issue , 2003, Pages

  Wiklund, Daniel ^a   Liu, Dake ^a  

^a LINKÖPING UNIVERSITY   (Sweden)

Author keywords

[No Author keywords available]

Indexed keywords

BANDWIDTH; COMPLEX NETWORKS; DISTRIBUTED COMPUTER SYSTEMS; DISTRIBUTED PARAMETER NETWORKS; EMBEDDED SYSTEMS; GATEWAYS (COMPUTER NETWORKS); INTERACTIVE COMPUTER SYSTEMS; INTERNET TELEPHONY; LOCKS (FASTENERS); MICROPROCESSOR CHIPS; NETWORK-ON-CHIP; SWITCHING CIRCUITS; SYSTEM-ON-CHIP; VLSI CIRCUITS; VOICE/DATA COMMUNICATION SYSTEMS;

ACCEPTABLE PERFORMANCE; AVAILABLE BANDWIDTH; COMMUNICATION INFRASTRUCTURE; GENERAL-PURPOSE COMPUTING; HARD REAL-TIME EMBEDDED SYSTEMS; HARD REAL-TIME SYSTEMS; TRAFFIC PATTERN; VOICE OVER IP;

REAL TIME SYSTEMS;

EID: 84947211640     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/IPDPS.2003.1213180     Document Type: Conference Paper

References (14)

1. ARM, Inc. , "AMBA bus description, " http://www. arm. com.
2. Daniel Wiklund and Dake Liu, "Switched interconnect for system-on-a-chip designs, " in Proc of the IP2000 Europe conference, 2000.
3. Iikka Saastamoinen, , and , "Interconnect IP node for future system-on-chip designs, " in IEEE int'l workshop on Electronic design, Test, and Applications, 2002.
4. M. Sgroi, M. Sheets, A. Mihal, K. Keutzer, S. Malik, J. Rabaey, and A. Sangiovanni-Vincentelli, "Addressing the system-on-chip interconnect woes through communicationbased design, " in Proc of the Design Automation Conference (DAC), 2001.
5. "IEC/ISO 7498-1 information technology-open systems interconnection-basic reference model: The basic model, " http://www. iso. org.
6. Hussein G. Badr and Sunil Podar, "An optimal shortestpath routing policy for network computers with regular mesh-connected topologies, " IEEE transactions on computers, vol. 38, no. 10, 1989.
7. Christopher J. Glass and Lionel M. Ni, "Fault-tolerant wormhole routing in meshes without virtual channels, " IEEE transactions on parallel and distributed systems, vol. 7, no. 6, 1996.
8. Pierre Guerrier and Alain Greiner, "A generic architecture for on-chip packet-switched interconnections, " in Proc of the Design and Test in Europe (DATE) conference, 2000.
9. Daniel Wiklund and Dake Liu, "Design of a system-onchip switched network and its design support, " in Proc of the Int'l conference on communications, circuits and systems (ICCCAS), 2002.
10. William J. Dally and Brian Towles, "Route packets, not wires: On-chip interconnection networks, " in Proc of the Design Automation Conference (DAC), 2001.
11. Christer Svensson, "Optimum voltage swing on onchip and off-chip interconnect, " IEEE Jounal of Solid-State Circuits, vol. 36, no. 7, pp. 1108-1112.
12. Peter Caputa and Christer Svensson, "Low power, low latency global interconnect, " in Proc of the 15th int'l ASIC/SoC conference, 2002.
13. William E. Witowsky and Dennis R. Gatens, "Carrier class, high density VoP, " Telogy Networks whitepaper, http://www. Telogy. com, 2002.
14. Jia Xu, "A comparison of priority scheduling and prerun-time scheduling, " in Proc of the Embedded Systems Conference in China, 2002.