Mapping and configuration methods for multi-use-case networks on chips

Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC

Volumn 2006, Issue , 2006, Pages 146-151

  Murali, Srinivasan ^a   Coenen, Martijn ^b   Radulescu, Andrei ^b   Goossens, Kees ^b   De Micheli, Giovanni ^c  

^a STANFORD UNIVERSITY   (United States)

^b PHILIPS RESEARCH LABORATORIES   (Netherlands)

^c EPFL   (Switzerland)

Author keywords

Best Effort; Dynamic; Frequency Scaling; Guaranteed Throughput; Multiple application platforms; Networks on chips; Reconfiguration; Systems on Chips; Use Cases; Voltage Scaling

Indexed keywords

ARCHITECTURAL DESIGN; ELECTRIC POTENTIAL; ELECTRIC POWER UTILIZATION; INTEGRATED CIRCUIT LAYOUT; MAPPING; TELECOMMUNICATION NETWORKS;

CONFIGURATION METHODS; DYNAMIC VOLTAGE; NETWORKS ON CHIPS (NOC); SYSTEMS ON CHIPS (SOC);

MICROPROCESSOR CHIPS;

EID: 33746910637     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/1118299.1118344     Document Type: Conference Paper

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